^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * IRQ definitions for Marvell MV78xx0 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __ASM_ARCH_IRQS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ASM_ARCH_IRQS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * MV78xx0 Low Interrupt Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IRQ_MV78XX0_ERR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IRQ_MV78XX0_SPI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IRQ_MV78XX0_I2C_0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IRQ_MV78XX0_I2C_1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IRQ_MV78XX0_IDMA_0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IRQ_MV78XX0_IDMA_1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IRQ_MV78XX0_IDMA_2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IRQ_MV78XX0_IDMA_3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IRQ_MV78XX0_TIMER_0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IRQ_MV78XX0_TIMER_1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IRQ_MV78XX0_TIMER_2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IRQ_MV78XX0_TIMER_3 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IRQ_MV78XX0_UART_0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IRQ_MV78XX0_UART_1 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IRQ_MV78XX0_UART_2 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IRQ_MV78XX0_UART_3 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IRQ_MV78XX0_USB_0 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IRQ_MV78XX0_USB_1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IRQ_MV78XX0_USB_2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IRQ_MV78XX0_CRYPTO 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IRQ_MV78XX0_SDIO_0 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IRQ_MV78XX0_SDIO_1 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IRQ_MV78XX0_XOR_0 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IRQ_MV78XX0_XOR_1 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IRQ_MV78XX0_I2S_0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IRQ_MV78XX0_I2S_1 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IRQ_MV78XX0_SATA 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IRQ_MV78XX0_TDMI 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * MV78xx0 High Interrupt Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IRQ_MV78XX0_PCIE_00 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IRQ_MV78XX0_PCIE_01 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IRQ_MV78XX0_PCIE_02 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IRQ_MV78XX0_PCIE_03 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IRQ_MV78XX0_PCIE_10 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IRQ_MV78XX0_PCIE_11 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IRQ_MV78XX0_PCIE_12 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IRQ_MV78XX0_PCIE_13 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IRQ_MV78XX0_GE00_SUM 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IRQ_MV78XX0_GE00_RX 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IRQ_MV78XX0_GE00_TX 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IRQ_MV78XX0_GE00_MISC 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IRQ_MV78XX0_GE01_SUM 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IRQ_MV78XX0_GE01_RX 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IRQ_MV78XX0_GE01_TX 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IRQ_MV78XX0_GE01_MISC 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IRQ_MV78XX0_GE10_SUM 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IRQ_MV78XX0_GE10_RX 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IRQ_MV78XX0_GE10_TX 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IRQ_MV78XX0_GE10_MISC 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IRQ_MV78XX0_GE11_SUM 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IRQ_MV78XX0_GE11_RX 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IRQ_MV78XX0_GE11_TX 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IRQ_MV78XX0_GE11_MISC 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IRQ_MV78XX0_GPIO_0_7 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IRQ_MV78XX0_GPIO_8_15 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IRQ_MV78XX0_GPIO_16_23 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IRQ_MV78XX0_GPIO_24_31 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IRQ_MV78XX0_DB_IN 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IRQ_MV78XX0_DB_OUT 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * MV78xx0 Error Interrupt Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IRQ_MV78XX0_GE_ERR 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * MV78XX0 General Purpose Pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IRQ_MV78XX0_GPIO_START 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define NR_GPIO_IRQS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MV78XX0_NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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