Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * arch/arm/mach-mv78xx0/irq.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * MV78xx0 IRQ handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <plat/orion-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <plat/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "bridge-regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static int __initdata gpio0_irqs[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	IRQ_MV78XX0_GPIO_0_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	IRQ_MV78XX0_GPIO_8_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	IRQ_MV78XX0_GPIO_16_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	IRQ_MV78XX0_GPIO_24_31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static asmlinkage void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __exception_irq_entry mv78xx0_legacy_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	if (stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		unsigned int hwirq = __fls(stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		handle_IRQ(hwirq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	if (stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		unsigned int hwirq = 32 + __fls(stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		handle_IRQ(hwirq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	if (stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		unsigned int hwirq = 64 + __fls(stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		handle_IRQ(hwirq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void __init mv78xx0_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	set_handle_irq(mv78xx0_legacy_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	 * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	 * registers for core #1 are at an offset of 0x18 from those of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	 * core #0.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 			mv78xx0_core_index() ? 0x18 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 			IRQ_MV78XX0_GPIO_START, gpio0_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }