^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-mv78xx0/db78x00-bp-setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Marvell DB-78x00-BP Development Board Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ata_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mv643xx_eth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "mv78xx0.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static struct mv643xx_eth_platform_data db78x00_ge00_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .phy_addr = MV643XX_ETH_PHY_ADDR(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct mv643xx_eth_platform_data db78x00_ge01_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .phy_addr = MV643XX_ETH_PHY_ADDR(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static struct mv643xx_eth_platform_data db78x00_ge10_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .phy_addr = MV643XX_ETH_PHY_ADDR(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct mv643xx_eth_platform_data db78x00_ge11_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .phy_addr = MV643XX_ETH_PHY_ADDR(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct mv_sata_platform_data db78x00_sata_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .n_ports = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct i2c_board_info __initdata db78x00_i2c_rtc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) I2C_BOARD_INFO("ds1338", 0x68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void __init db78x00_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Basic MV78xx0 setup. Needs to be called early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mv78xx0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Partition on-chip peripherals between the two CPU cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (mv78xx0_core_index() == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mv78xx0_ehci0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) mv78xx0_ehci1_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mv78xx0_ehci2_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mv78xx0_ge00_init(&db78x00_ge00_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) mv78xx0_ge01_init(&db78x00_ge01_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mv78xx0_ge10_init(&db78x00_ge10_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) mv78xx0_ge11_init(&db78x00_ge11_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mv78xx0_sata_init(&db78x00_sata_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mv78xx0_uart0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mv78xx0_uart2_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mv78xx0_i2c_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) i2c_register_board_info(0, &db78x00_i2c_rtc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mv78xx0_uart1_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mv78xx0_uart3_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int __init db78x00_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (machine_is_db78x00_bp()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Assign the x16 PCIe slot on the board to CPU core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * #0, and let CPU core #1 have the four x1 slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (mv78xx0_core_index() == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mv78xx0_pcie_init(0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mv78xx0_pcie_init(1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) subsys_initcall(db78x00_pci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .nr_irqs = MV78XX0_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .init_machine = db78x00_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .map_io = mv78xx0_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .init_early = mv78xx0_init_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .init_irq = mv78xx0_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .init_time = mv78xx0_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .restart = mv78xx0_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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