Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * arch/arm/mach-mv78xx0/common.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Core functions for Marvell MV78xx0 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/ata_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/hardware/cache-feroceon-l2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/platform_data/usb-ehci-orion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/platform_data/mtd-orion_nand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <plat/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <plat/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <plat/addr-map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include "mv78xx0.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include "bridge-regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static int get_tclk(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * Common bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) int mv78xx0_core_index(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u32 extra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	 * Read Extra Features register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return !!(extra & 0x00004000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static int get_hclk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	 * HCLK tick rate is configured by DEV_D[7:5] pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		hclk = 166666667;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		hclk = 200000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		hclk = 266666667;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		hclk = 333333333;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		hclk = 400000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		panic("unknown HCLK PLL setting: %.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			readl(SAMPLE_AT_RESET_LOW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * PCLK/L2CLK by bits [19:14].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (core_index == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	*pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	 * ratio (1, 2, 3).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	*l2clk = *pclk / (((cfg >> 4) & 3) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int get_tclk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	int tclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	 * TCLK tick rate is configured by DEV_A[2:0] strap pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		tclk_freq = 166666667;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		tclk_freq = 200000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		panic("unknown TCLK PLL setting: %.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			readl(SAMPLE_AT_RESET_HIGH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return tclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * I/O Address Mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct map_desc mv78xx0_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		.virtual	= (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.pfn		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.length		= MV78XX0_CORE_REGS_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.type		= MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.virtual	= (unsigned long) MV78XX0_REGS_VIRT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.pfn		= __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.length		= MV78XX0_REGS_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.type		= MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void __init mv78xx0_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	unsigned long phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 * Map the right set of per-core registers depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 * which core we are running on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (mv78xx0_core_index() == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		phys = MV78XX0_CORE0_REGS_PHYS_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		phys = MV78XX0_CORE1_REGS_PHYS_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * CLK tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct clk *tclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void __init clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, get_tclk());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	orion_clkdev_init(tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * EHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void __init mv78xx0_ehci0_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  * EHCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) void __init mv78xx0_ehci1_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  * EHCI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) void __init mv78xx0_ehci2_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * GE00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	orion_ge00_init(eth_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			IRQ_MV78XX0_GE_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			MV643XX_TX_CSUM_DEFAULT_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * GE01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	orion_ge01_init(eth_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			MV643XX_TX_CSUM_DEFAULT_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  * GE10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	u32 dev, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * On the Z0, ge10 and ge11 are internally connected back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 * to back, and not brought out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	mv78xx0_pcie_id(&dev, &rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (dev == MV78X00_Z0_DEV_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		eth_data->speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		eth_data->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	orion_ge10_init(eth_data, GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  * GE11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	u32 dev, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 * On the Z0, ge10 and ge11 are internally connected back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 * to back, and not brought out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	mv78xx0_pcie_id(&dev, &rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (dev == MV78X00_Z0_DEV_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		eth_data->speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		eth_data->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	orion_ge11_init(eth_data, GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void __init mv78xx0_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  * SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  * UART0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void __init mv78xx0_uart0_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			 IRQ_MV78XX0_UART_0, tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)  * UART1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) void __init mv78xx0_uart1_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			 IRQ_MV78XX0_UART_1, tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  * UART2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) void __init mv78xx0_uart2_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			 IRQ_MV78XX0_UART_2, tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  * UART3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) void __init mv78xx0_uart3_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			 IRQ_MV78XX0_UART_3, tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)  * Time handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void __init mv78xx0_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	orion_time_set_base(TIMER_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (mv78xx0_core_index() == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		mvebu_mbus_init("marvell,mv78xx0-mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 				BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 				DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		mvebu_mbus_init("marvell,mv78xx0-mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 				BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 				DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) void __ref mv78xx0_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			IRQ_MV78XX0_TIMER_1, get_tclk());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)  * General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static char * __init mv78xx0_id(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	u32 dev, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	mv78xx0_pcie_id(&dev, &rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (dev == MV78X00_Z0_DEV_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		if (rev == MV78X00_REV_Z0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			return "MV78X00-Z0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			return "MV78X00-Rev-Unsupported";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	} else if (dev == MV78100_DEV_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		if (rev == MV78100_REV_A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			return "MV78100-A0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		else if (rev == MV78100_REV_A1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			return "MV78100-A1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			return "MV78100-Rev-Unsupported";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	} else if (dev == MV78200_DEV_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		if (rev == MV78100_REV_A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 			return "MV78200-A0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			return "MV78200-Rev-Unsupported";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		return "Device-Unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int __init is_l2_writethrough(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) void __init mv78xx0_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	int core_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	int hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	int pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	int l2clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	core_index = mv78xx0_core_index();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	hclk = get_hclk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	printk(KERN_INFO "%s ", mv78xx0_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	printk("core #%d, ", core_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	if (IS_ENABLED(CONFIG_CACHE_FEROCEON_L2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		feroceon_l2_init(is_l2_writethrough());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	/* Setup root of clk tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	 * Enable soft reset to assert RSTOUTn.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	 * Assert soft reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	writel(SOFT_RESET, SYSTEM_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }