^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Buffalo WXL (Terastation Duo) Setup routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * sebastien requiem <sebastien@requiem.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ata_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mv643xx_eth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "mv78xx0.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "mpp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* This arch has 2 Giga Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static struct mv643xx_eth_platform_data db78x00_ge00_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .phy_addr = MV643XX_ETH_PHY_ADDR(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct mv643xx_eth_platform_data db78x00_ge01_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .phy_addr = MV643XX_ETH_PHY_ADDR(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* 2 SATA controller supporting HotPlug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct mv_sata_platform_data db78x00_sata_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .n_ports = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct i2c_board_info __initdata db78x00_i2c_rtc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) I2C_BOARD_INFO("ds1338", 0x68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static unsigned int wxl_mpp_config[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MPP0_GE1_TXCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MPP1_GE1_TXCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MPP2_GE1_RXCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MPP3_GE1_RXCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MPP4_GE1_TXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MPP5_GE1_TXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MPP6_GE1_TXD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MPP7_GE1_TXD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MPP8_GE1_RXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MPP9_GE1_RXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MPP10_GE1_RXD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MPP11_GE1_RXD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MPP12_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MPP13_SYSRST_OUTn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MPP14_SATA1_ACTn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MPP15_SATA0_ACTn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MPP16_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MPP17_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MPP18_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MPP19_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MPP20_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MPP21_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MPP22_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MPP23_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MPP24_UA2_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MPP25_UA2_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MPP26_UA2_CTSn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MPP27_UA2_RTSn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MPP28_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MPP29_SYSRST_OUTn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MPP30_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MPP31_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MPP32_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MPP33_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MPP34_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MPP35_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MPP36_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MPP37_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MPP38_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MPP39_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MPP40_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MPP41_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MPP42_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MPP43_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MPP44_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MPP45_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MPP46_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MPP47_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MPP48_SATA1_ACTn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MPP49_SATA0_ACTn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void __init wxl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Basic MV78xx0 setup. Needs to be called early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mv78xx0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mv78xx0_mpp_conf(wxl_mpp_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Partition on-chip peripherals between the two CPU cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mv78xx0_ehci0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mv78xx0_ehci1_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mv78xx0_ehci2_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mv78xx0_ge00_init(&db78x00_ge00_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mv78xx0_ge01_init(&db78x00_ge01_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mv78xx0_sata_init(&db78x00_sata_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mv78xx0_uart0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mv78xx0_uart1_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mv78xx0_uart2_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mv78xx0_uart3_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mv78xx0_i2c_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) i2c_register_board_info(0, &db78x00_i2c_rtc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int __init wxl_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (machine_is_terastation_wxl()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * Assign the x16 PCIe slot on the board to CPU core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * #0, and let CPU core #1 have the four x1 slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (mv78xx0_core_index() == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mv78xx0_pcie_init(0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mv78xx0_pcie_init(1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) subsys_initcall(wxl_pci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Maintainer: Sebastien Requiem <sebastien@requiem.fr> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .nr_irqs = MV78XX0_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .init_machine = wxl_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .map_io = mv78xx0_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .init_early = mv78xx0_init_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .init_irq = mv78xx0_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .init_time = mv78xx0_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .restart = mv78xx0_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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