Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __ASM_ARCH_BRIDGE_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __ASM_ARCH_BRIDGE_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "mv78xx0.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CPU_CONTROL		(BRIDGE_VIRT_BASE + 0x0104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define L2_WRITETHROUGH		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RSTOUTn_MASK_PHYS	(BRIDGE_PHYS_BASE + 0x0108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SOFT_RESET_OUT_EN	0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SOFT_RESET		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BRIDGE_INT_TIMER1_CLR	(~0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IRQ_CAUSE_ERR_OFF	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IRQ_CAUSE_LOW_OFF	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IRQ_CAUSE_HIGH_OFF	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IRQ_MASK_ERR_OFF	0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IRQ_MASK_LOW_OFF	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IRQ_MASK_HIGH_OFF	0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TIMER_PHYS_BASE		(BRIDGE_PHYS_BASE + 0x0300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif