Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Device Tree support for MStar/Sigmastar Armv7 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2020 thingy.jp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: Daniel Palmer <daniel@thingy.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * In the u-boot code the area these registers are in is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * called "L3 bridge" and there are register descriptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * for something in the same area called "AXI".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * It's not exactly known what this is but the vendor code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * for both u-boot and linux share calls to "flush the miu pipe".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * This seems to be to force pending CPU writes to memory so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * the state is right before DMA capable devices try to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * descriptors and data the CPU has prepared. Without doing this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * ethernet doesn't work reliably for example.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MSTARV7_L3BRIDGE_FLUSH		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MSTARV7_L3BRIDGE_STATUS		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MSTARV7_L3BRIDGE_FLUSH_TRIGGER	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MSTARV7_L3BRIDGE_STATUS_DONE	BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void __iomem *l3bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const char * const mstarv7_board_dt_compat[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	"mstar,infinity",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	"mstar,infinity3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	"mstar,mercury5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  * This may need locking to deal with situations where an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  * happens while we are in here and mb() gets called by the interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)  * The vendor code did have a spin lock but it doesn't seem to be needed and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)  * removing it hasn't caused any side effects so far.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)  * [writel|readl]_relaxed have to be used here because otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)  * we'd end up right back in here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void mstarv7_mb(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	/* toggle the flush miu pipe fire bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	writel_relaxed(0, l3bridge + MSTARV7_L3BRIDGE_FLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, l3bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			+ MSTARV7_L3BRIDGE_FLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	while (!(readl_relaxed(l3bridge + MSTARV7_L3BRIDGE_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			& MSTARV7_L3BRIDGE_STATUS_DONE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		/* wait for flush to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void __init mstarv7_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	np = of_find_compatible_node(NULL, NULL, "mstar,l3bridge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	l3bridge = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	if (l3bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 		soc_mb = mstarv7_mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 		pr_warn("Failed to install memory barrier, DMA will be broken!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	.dt_compat	= mstarv7_board_dt_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	.init_machine	= mstarv7_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MACHINE_END