^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support for the Marvell PXA168 Teton BGA Development Platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef __ASM_MACH_TETON_BGA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define __ASM_MACH_TETON_BGA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define MMC_PWENA_GPIO 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define USBHPENB_GPIO 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RTC_INT_GPIO 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define LCD_VBLK_EN_GPIO 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define LCD_DVDD_EN_GPIO 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RST_WIFI_GPIO 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CF_PWEN_GPIO 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define USB_OC_GPIO 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PWM_GPIO 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define USBHPENA_GPIO 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TS_INT_GPIO 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CIR_GPIO 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #endif /* __ASM_MACH_TETON_BGA_H */