^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __ASM_ARCH_REGS_USB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __ASM_ARCH_REGS_USB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define PXA168_U2O_REGBASE (0xd4208000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PXA168_U2O_PHYBASE (0xd4207000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PXA168_U2H_REGBASE (0xd4209000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PXA168_U2H_PHYBASE (0xd4206000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MMP3_HSIC1_REGBASE (0xf0001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MMP3_HSIC1_PHYBASE (0xf0001800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MMP3_HSIC2_REGBASE (0xf0002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MMP3_HSIC2_PHYBASE (0xf0002800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MMP3_FSIC_REGBASE (0xf0003000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MMP3_FSIC_PHYBASE (0xf0003800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define USB_REG_RANGE (0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define USB_PHY_RANGE (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define U2x_CAPREGS_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* phy regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UTMI_REVISION 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UTMI_CTRL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UTMI_PLL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UTMI_TX 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UTMI_RX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UTMI_IVREF 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define UTMI_T0 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define UTMI_T1 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define UTMI_T2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UTMI_T3 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define UTMI_T4 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UTMI_T5 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define UTMI_RESERVE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UTMI_USB_INT 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define UTMI_DBG_CTL 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UTMI_OTG_ADDON 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* For UTMICTRL Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UTMI_CTRL_USB_CLK_EN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* pxa168 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define UTMI_CTRL_SUSPEND_SET1 (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define UTMI_CTRL_SUSPEND_SET2 (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define UTMI_CTRL_RXBUF_PDWN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define UTMI_CTRL_TXBUF_PDWN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define UTMI_CTRL_INPKT_DELAY_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define UTMI_CTRL_PU_REF_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UTMI_CTRL_ARC_PULLDN_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define UTMI_CTRL_PLL_PWR_UP_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define UTMI_CTRL_PWR_UP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* For UTMI_PLL Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define UTMI_PLL_PLLCALI12_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define UTMI_PLL_PLLCALI12_MASK (0x3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define UTMI_PLL_PLLVDD18_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define UTMI_PLL_PLLVDD18_MASK (0x3 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define UTMI_PLL_PLLVDD12_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define UTMI_PLL_PLLVDD12_MASK (0x3 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define UTMI_PLL_CLK_BLK_EN_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_BLK_EN (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PLL_READY (0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define KVCO_EXT (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define VCOCAL_START (0x1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define UTMI_PLL_KVCO_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define UTMI_PLL_KVCO_MASK (0x7 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define UTMI_PLL_ICP_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define UTMI_PLL_ICP_MASK (0x7 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define UTMI_PLL_FBDIV_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define UTMI_PLL_FBDIV_MASK (0xFF << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define UTMI_PLL_REFDIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define UTMI_PLL_REFDIV_MASK (0xF << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* For UTMI_TX Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define UTMI_TX_REG_EXT_FS_RCAL_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define UTMI_TX_REG_EXT_FS_RCAL_MASK (0xf << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define UTMI_TX_TXVDD12_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define UTMI_TX_TXVDD12_MASK (0x3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define UTMI_TX_CK60_PHSEL_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define UTMI_TX_CK60_PHSEL_MASK (0xf << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define UTMI_TX_IMPCAL_VTH_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define UTMI_TX_IMPCAL_VTH_MASK (0x7 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define REG_RCAL_START (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define UTMI_TX_LOW_VDD_EN_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define UTMI_TX_AMP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define UTMI_TX_AMP_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* For UTMI_RX Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define UTMI_REG_SQ_LENGTH_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define UTMI_REG_SQ_LENGTH_MASK (0x3 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define UTMI_RX_SQ_THRESH_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define UTMI_RX_SQ_THRESH_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define UTMI_OTG_ADDON_OTG_ON (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* fsic registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define FSIC_MISC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define FSIC_INT 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define FSIC_CTRL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* HSIC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HSIC_PAD_CTRL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HSIC_CTRL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HSIC_CTRL_HSIC_ENABLE (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HSIC_CTRL_PLL_BYPASS (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEST_GRP_0 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEST_GRP_1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HSIC_INT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HSIC_INT_READY_INT_EN (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HSIC_INT_CONNECT_INT_EN (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HSIC_INT_CORE_INT_EN (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HSIC_INT_HS_READY (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HSIC_INT_CONNECT (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HSIC_INT_CORE (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HSIC_CONFIG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define USBHSIC_CTRL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HSIC_USB_CTRL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HSIC_USB_CTRL_CLKEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HSIC_USB_CLK_PHY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HSIC_USB_CLK_PMU 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #endif /* __ASM_ARCH_PXA_U2O_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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