Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *   Timers Module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __ASM_MACH_REGS_TIMERS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __ASM_MACH_REGS_TIMERS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "addr-map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define TIMERS1_VIRT_BASE	(APB_VIRT_BASE + 0x14000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TIMERS2_VIRT_BASE	(APB_VIRT_BASE + 0x16000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TMR_CCR		(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TMR_TN_MM(n, m)	(0x0004 + ((n) << 3) + (((n) + (m)) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TMR_CR(n)	(0x0028 + ((n) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TMR_SR(n)	(0x0034 + ((n) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TMR_IER(n)	(0x0040 + ((n) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TMR_PLVR(n)	(0x004c + ((n) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TMR_PLCR(n)	(0x0058 + ((n) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TMR_WMER	(0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TMR_WMR		(0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TMR_WVR		(0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TMR_WSR		(0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TMR_ICR(n)	(0x0074 + ((n) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TMR_WICR	(0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TMR_CER		(0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TMR_CMR		(0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TMR_ILR(n)	(0x008c + ((n) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TMR_WCR		(0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TMR_WFAR	(0x009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TMR_WSAR	(0x00A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TMR_CVWR(n)	(0x00A4 + ((n) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TMR_CCR_CS_0(x)	(((x) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TMR_CCR_CS_1(x)	(((x) & 0x7) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TMR_CCR_CS_2(x)	(((x) & 0x3) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif /* __ASM_MACH_REGS_TIMERS_H */