Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *   Interrupt Control Unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __ASM_MACH_ICU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __ASM_MACH_ICU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "addr-map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ICU_VIRT_BASE	(AXI_VIRT_BASE + 0x82000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ICU_REG(x)	(ICU_VIRT_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ICU2_VIRT_BASE	(AXI_VIRT_BASE + 0x84000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ICU2_REG(x)	(ICU2_VIRT_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ICU_INT_CONF(n)		ICU_REG((n) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ICU_INT_CONF_MASK	(0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /************ PXA168/PXA910 (MMP) *********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ICU_INT_CONF_AP_INT	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ICU_INT_CONF_CP_INT	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ICU_INT_CONF_IRQ	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ICU_AP_FIQ_SEL_INT_NUM	ICU_REG(0x108)	/* AP FIQ Selected Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ICU_AP_IRQ_SEL_INT_NUM	ICU_REG(0x10C)	/* AP IRQ Selected Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ICU_AP_GBL_IRQ_MSK	ICU_REG(0x114)	/* AP Global Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ICU_INT_STATUS_0	ICU_REG(0x128)	/* Interrupt Stuats 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ICU_INT_STATUS_1	ICU_REG(0x12C)	/* Interrupt Status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /************************** MMP2 ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * IRQ0/FIQ0 is routed to SP IRQ/FIQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ICU_INT_ROUTE_SP_IRQ		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ICU_INT_ROUTE_PJ4_IRQ		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ICU_INT_ROUTE_PJ4_FIQ		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MMP2_ICU_PJ4_IRQ_STATUS0	ICU_REG(0x138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MMP2_ICU_PJ4_IRQ_STATUS1	ICU_REG(0x13c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MMP2_ICU_PJ4_FIQ_STATUS0	ICU_REG(0x140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MMP2_ICU_PJ4_FIQ_STATUS1	ICU_REG(0x144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MMP2_ICU_INT4_STATUS		ICU_REG(0x150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MMP2_ICU_INT5_STATUS		ICU_REG(0x154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MMP2_ICU_INT17_STATUS		ICU_REG(0x158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MMP2_ICU_INT35_STATUS		ICU_REG(0x15c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MMP2_ICU_INT51_STATUS		ICU_REG(0x160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MMP2_ICU_INT4_MASK		ICU_REG(0x168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MMP2_ICU_INT5_MASK		ICU_REG(0x16C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MMP2_ICU_INT17_MASK		ICU_REG(0x170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MMP2_ICU_INT35_MASK		ICU_REG(0x174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MMP2_ICU_INT51_MASK		ICU_REG(0x178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MMP2_ICU_SP_IRQ_SEL		ICU_REG(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MMP2_ICU_PJ4_IRQ_SEL		ICU_REG(0x104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MMP2_ICU_PJ4_FIQ_SEL		ICU_REG(0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MMP2_ICU_INVERT			ICU_REG(0x164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MMP2_ICU_INV_PMIC		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MMP2_ICU_INV_PERF		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MMP2_ICU_INV_COMMTX		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MMP2_ICU_INV_COMMRX		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* __ASM_MACH_ICU_H */