^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Application Subsystem Power Management Unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __ASM_MACH_REGS_APMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __ASM_MACH_REGS_APMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "addr-map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define APMU_FNCLK_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define APMU_AXICLK_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define APMU_FNRST_DIS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define APMU_AXIRST_DIS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Wake Clear Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define APMU_WAKE_CLR APMU_REG(0x07c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define APMU_PXA168_KP_WAKE_CLR (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define APMU_PXA168_CFI_WAKE_CLR (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define APMU_PXA168_XD_WAKE_CLR (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define APMU_PXA168_MSP_WAKE_CLR (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define APMU_PXA168_SD4_WAKE_CLR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define APMU_PXA168_SD3_WAKE_CLR (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define APMU_PXA168_SD2_WAKE_CLR (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define APMU_PXA168_SD1_WAKE_CLR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif /* __ASM_MACH_REGS_APMU_H */