^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-mmp/pxa910.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Code specific to PXA910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk/mmp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqchip/mmp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/hardware/cache-tauros2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "addr-map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "regs-apbc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/soc/mmp/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "mfp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "pm-pxa910.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "pxa910.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MFP_ADDR_X(GPIO0, GPIO54, 0xdc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MFP_ADDR_X(GPIO67, GPIO98, 0x1b8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MFP_ADDR_X(GPIO100, GPIO109, 0x238),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MFP_ADDR(GPIO123, 0xcc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MFP_ADDR(GPIO124, 0xd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MFP_ADDR(DF_IO0, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MFP_ADDR(DF_IO1, 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MFP_ADDR(DF_IO2, 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MFP_ADDR(DF_IO3, 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MFP_ADDR(DF_IO4, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MFP_ADDR(DF_IO5, 0x2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MFP_ADDR(DF_IO6, 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MFP_ADDR(DF_IO7, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MFP_ADDR(DF_IO8, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MFP_ADDR(DF_IO9, 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MFP_ADDR(DF_IO10, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MFP_ADDR(DF_IO11, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MFP_ADDR(DF_IO12, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MFP_ADDR(DF_IO13, 0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MFP_ADDR(DF_IO14, 0x8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MFP_ADDR(DF_IO15, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MFP_ADDR(DF_nCS0_SM_nCS2, 0x44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MFP_ADDR(DF_nCS1_SM_nCS3, 0x48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MFP_ADDR(SM_nCS0, 0x4c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MFP_ADDR(SM_nCS1, 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MFP_ADDR(DF_WEn, 0x54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MFP_ADDR(DF_REn, 0x58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MFP_ADDR(DF_CLE_SM_OEn, 0x5c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MFP_ADDR(DF_ALE_SM_WEn, 0x60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MFP_ADDR(SM_SCLK, 0x64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MFP_ADDR(DF_RDY0, 0x68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MFP_ADDR(SM_BE0, 0x6c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MFP_ADDR(SM_BE1, 0x70),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MFP_ADDR(SM_ADV, 0x74),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MFP_ADDR(DF_RDY1, 0x78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MFP_ADDR(SM_ADVMUX, 0x7c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MFP_ADDR(SM_RDY, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MFP_ADDR_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void __init pxa910_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) icu_init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) icu_irq_chip.irq_set_wake = pxa910_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int __init pxa910_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (cpu_is_pxa910()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #ifdef CONFIG_CACHE_TAUROS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) tauros2_init(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mfp_init_base(MFPR_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mfp_init_addr(pxa910_mfp_addr_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pxa910_clk_init(APB_PHYS_BASE + 0x50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) AXI_PHYS_BASE + 0x82800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) APB_PHYS_BASE + 0x15000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) APB_PHYS_BASE + 0x3b000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) postcore_initcall(pxa910_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* system timer - clock enabled, 3.25MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define APBC_TIMERS APBC_REG(0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void __init pxa910_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* reset and configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mmp_timer_init(IRQ_PXA910_AP1_TIMER1, 3250000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* on-chip devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* NOTE: there are totally 3 UARTs on PXA910:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * UART1 - Slow UART (can be used both by AP and CP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * UART2/3 - Fast UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * To be backward compatible with the legacy FFUART/BTUART/STUART sequence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * they are re-ordered as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * pxa910_device_uart1 - UART2 as FFUART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * pxa910_device_uart2 - UART3 as BTUART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * UART1 is not used by AP for the moment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PXA910_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PXA910_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PXA910_DEVICE(pwm1, "pxa910-pwm", 0, NONE, 0xd401a000, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PXA910_DEVICE(disp, "mmp-disp", 0, LCD, 0xd420b000, 0x1ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PXA910_DEVICE(fb, "mmp-fb", -1, NONE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PXA910_DEVICE(panel, "tpo-hvga", -1, NONE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct resource pxa910_resource_gpio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .start = 0xd4019000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .end = 0xd4019fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .start = IRQ_PXA910_AP_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .end = IRQ_PXA910_AP_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .name = "gpio_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct platform_device pxa910_device_gpio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .name = "mmp-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .num_resources = ARRAY_SIZE(pxa910_resource_gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .resource = pxa910_resource_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static struct resource pxa910_resource_rtc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .start = 0xd4010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .end = 0xd401003f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .start = IRQ_PXA910_RTC_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .end = IRQ_PXA910_RTC_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .name = "rtc 1Hz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .start = IRQ_PXA910_RTC_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .end = IRQ_PXA910_RTC_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .name = "rtc alarm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct platform_device pxa910_device_rtc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .name = "sa1100-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .num_resources = ARRAY_SIZE(pxa910_resource_rtc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .resource = pxa910_resource_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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