^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PXA910 Power Management Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) Copyright 2009 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __PXA910_PM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __PXA910_PM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define APMU_MOH_IDLE_CFG APMU_REG(0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MPMU_FCCR MPMU_REG(0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MPMU_APCR MPMU_REG(0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MPMU_APCR_AXISD (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MPMU_APCR_DSPSD (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MPMU_APCR_SLPEN (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MPMU_APCR_DTCMSD (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MPMU_APCR_DDRCORSD (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MPMU_APCR_APBSD (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MPMU_APCR_BBSD (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MPMU_APCR_SLPWP0 (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MPMU_APCR_SLPWP1 (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MPMU_APCR_SLPWP2 (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MPMU_APCR_SLPWP3 (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MPMU_APCR_VCTCXOSD (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MPMU_APCR_SLPWP4 (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MPMU_APCR_SLPWP5 (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MPMU_APCR_SLPWP6 (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MPMU_APCR_SLPWP7 (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MPMU_APCR_MSASLPEN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MPMU_APCR_STBYEN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MPMU_AWUCRM MPMU_REG(0x104c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MPMU_AWUCRM_SDH1 (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MPMU_AWUCRM_SDH2 (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MPMU_AWUCRM_KEYPRESS (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MPMU_AWUCRM_TRACKBALL (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MPMU_AWUCRM_NEWROTARY (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MPMU_AWUCRM_RTC_ALARM (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) POWER_MODE_ACTIVE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) POWER_MODE_CORE_INTIDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) POWER_MODE_CORE_EXTIDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) POWER_MODE_APPS_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) POWER_MODE_APPS_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) POWER_MODE_SYS_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) POWER_MODE_HIBERNATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) POWER_MODE_UDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) extern int pxa910_set_wake(struct irq_data *data, unsigned int on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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