Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * MMP2 Power Management Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * (C) Copyright 2010 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __MMP2_PM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __MMP2_PM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "addr-map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define APMU_PJ_IDLE_CFG			APMU_REG(0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define APMU_PJ_IDLE_CFG_PJ_IDLE		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define APMU_PJ_IDLE_CFG_PJ_PWRDWN		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define APMU_PJ_IDLE_CFG_PWR_SW(x)		((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define APMU_PJ_IDLE_CFG_L2_PWR_SW		(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK	(3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define APMU_SRAM_PWR_DWN			APMU_REG(0x08c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MPMU_SCCR				MPMU_REG(0x038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MPMU_PCR_PJ				MPMU_REG(0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MPMU_PCR_PJ_AXISD			(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MPMU_PCR_PJ_SLPEN			(1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MPMU_PCR_PJ_SPSD			(1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MPMU_PCR_PJ_DDRCORSD			(1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MPMU_PCR_PJ_APBSD			(1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MPMU_PCR_PJ_INTCLR			(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MPMU_PCR_PJ_SLPWP0			(1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MPMU_PCR_PJ_SLPWP1			(1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MPMU_PCR_PJ_SLPWP2			(1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MPMU_PCR_PJ_SLPWP3			(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MPMU_PCR_PJ_VCTCXOSD			(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MPMU_PCR_PJ_SLPWP4			(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MPMU_PCR_PJ_SLPWP5			(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MPMU_PCR_PJ_SLPWP6			(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MPMU_PCR_PJ_SLPWP7			(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MPMU_PLL2_CTRL1				MPMU_REG(0x0414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MPMU_CGR_PJ				MPMU_REG(0x1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MPMU_WUCRM_PJ				MPMU_REG(0x104c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MPMU_WUCRM_PJ_WAKEUP(x)			(1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MPMU_WUCRM_PJ_RTC_ALARM			(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	POWER_MODE_ACTIVE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	POWER_MODE_CORE_INTIDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	POWER_MODE_CORE_EXTIDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	POWER_MODE_APPS_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	POWER_MODE_APPS_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	POWER_MODE_CHIP_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	POWER_MODE_SYS_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) extern void mmp2_pm_enter_lowpower_mode(int state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) extern int mmp2_set_wake(struct irq_data *d, unsigned int on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif