Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * MMP2 Power Management Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * (C) Copyright 2012 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/soc/mmp/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "addr-map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "pm-mmp2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "regs-icu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) int mmp2_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	unsigned long data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	/* enable wakeup sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	switch (irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	case IRQ_MMP2_RTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	case IRQ_MMP2_RTC_ALARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		data = MPMU_WUCRM_PJ_WAKEUP(4) | MPMU_WUCRM_PJ_RTC_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	case IRQ_MMP2_PMIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		data = MPMU_WUCRM_PJ_WAKEUP(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	case IRQ_MMP2_MMC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		/* mmc use WAKEUP2, same as GPIO wakeup source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		data = MPMU_WUCRM_PJ_WAKEUP(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			data |= __raw_readl(MPMU_WUCRM_PJ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			__raw_writel(data, MPMU_WUCRM_PJ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			data = ~data & __raw_readl(MPMU_WUCRM_PJ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			__raw_writel(data, MPMU_WUCRM_PJ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static void pm_scu_clk_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* close AXI fabric clock gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	__raw_writel(0x0, CIU_REG(0x64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	__raw_writel(0x0, CIU_REG(0x68));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* close MCB master clock gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	val = __raw_readl(CIU_REG(0x1c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	val |= 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	__raw_writel(val, CIU_REG(0x1c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static void pm_scu_clk_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* open AXI fabric clock gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	__raw_writel(0x03003003, CIU_REG(0x64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	__raw_writel(0x00303030, CIU_REG(0x68));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/* open MCB master clock gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	val = __raw_readl(CIU_REG(0x1c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	val &= ~(0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	__raw_writel(val, CIU_REG(0x1c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	return ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static void pm_mpmu_clk_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * disable clocks in MPMU_CGR_PJ register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 * except clock for APMU_PLL1, APMU_PLL1_2 and AP_26M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	__raw_writel(0x0000a010, MPMU_CGR_PJ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void pm_mpmu_clk_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	__raw_writel(0xdffefffe, MPMU_CGR_PJ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	val = __raw_readl(MPMU_PLL2_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	val |= (1 << 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	__raw_writel(val, MPMU_PLL2_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void mmp2_pm_enter_lowpower_mode(int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	uint32_t idle_cfg, apcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	idle_cfg = __raw_readl(APMU_PJ_IDLE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	apcr = __raw_readl(MPMU_PCR_PJ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD | MPMU_PCR_PJ_APBSD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		 | MPMU_PCR_PJ_AXISD | MPMU_PCR_PJ_VCTCXOSD | (1 << 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	idle_cfg &= ~APMU_PJ_IDLE_CFG_PJ_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	case POWER_MODE_SYS_SLEEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		apcr |= MPMU_PCR_PJ_SLPEN;		/* set the SLPEN bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		apcr |= MPMU_PCR_PJ_VCTCXOSD;		/* set VCTCXOSD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	case POWER_MODE_CHIP_SLEEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		apcr |= MPMU_PCR_PJ_SLPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	case POWER_MODE_APPS_SLEEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		apcr |= MPMU_PCR_PJ_APBSD;		/* set APBSD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	case POWER_MODE_APPS_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		apcr |= MPMU_PCR_PJ_AXISD;		/* set AXISDD bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		apcr |= MPMU_PCR_PJ_DDRCORSD;		/* set DDRCORSD bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		idle_cfg |= APMU_PJ_IDLE_CFG_PJ_PWRDWN;	/* PJ power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		apcr |= MPMU_PCR_PJ_SPSD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	case POWER_MODE_CORE_EXTIDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		idle_cfg |= APMU_PJ_IDLE_CFG_PJ_IDLE;	/* set the IDLE bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		idle_cfg &= ~APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		idle_cfg |= APMU_PJ_IDLE_CFG_PWR_SW(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			| APMU_PJ_IDLE_CFG_L2_PWR_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	case POWER_MODE_CORE_INTIDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		apcr &= ~MPMU_PCR_PJ_SPSD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/* set reserve bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	apcr |= (1 << 30) | (1 << 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* finally write the registers back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	__raw_writel(idle_cfg, APMU_PJ_IDLE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	__raw_writel(apcr, MPMU_PCR_PJ);	/* 0xfe086000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int mmp2_pm_enter(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	temp = __raw_readl(MMP2_ICU_INT4_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (temp & (1 << 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		printk(KERN_ERR "%s: PMIC interrupt is handling\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	temp = __raw_readl(APMU_SRAM_PWR_DWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	temp |= ((1 << 19) | (1 << 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	__raw_writel(temp, APMU_SRAM_PWR_DWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	pm_mpmu_clk_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	pm_scu_clk_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	printk(KERN_INFO "%s: before suspend\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	printk(KERN_INFO "%s: after suspend\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	pm_mpmu_clk_enable();		/* enable clocks in MPMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	pm_scu_clk_enable();		/* enable clocks in SCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  * Called after processes are frozen, but before we shut down devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int mmp2_pm_prepare(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	mmp2_pm_enter_lowpower_mode(POWER_MODE_SYS_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  * Called after devices are re-setup, but before processes are thawed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void mmp2_pm_finish(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	mmp2_pm_enter_lowpower_mode(POWER_MODE_CORE_INTIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int mmp2_pm_valid(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return ((state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct platform_suspend_ops mmp2_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.valid		= mmp2_pm_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.prepare	= mmp2_pm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.enter		= mmp2_pm_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.finish		= mmp2_pm_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int __init mmp2_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	uint32_t apcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (!cpu_is_mmp2())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	suspend_set_ops(&mmp2_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 * Set bit 0, Slow clock Select 32K clock input instead of VCXO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 * VCXO is chosen by default, which would be disabled in suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	__raw_writel(0x5, MPMU_SCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 * Clear bit 23 of CIU_CPU_CONF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * direct PJ4 to DDR access through Memory Controller slow queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * fast queue has issue and cause lcd will flick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	__raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* Clear default low power control bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	apcr = __raw_readl(MPMU_PCR_PJ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			| MPMU_PCR_PJ_APBSD | MPMU_PCR_PJ_AXISD | 1 << 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	__raw_writel(apcr, MPMU_PCR_PJ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) late_initcall(mmp2_pm_init);