Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <asm/smp_scu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include "addr-map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SW_BRANCH_VIRT_ADDR	CIU_REG(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static int mmp3_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	 * Apparently, the boot ROM on the second core spins on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	 * register becoming non-zero and then jumps to the address written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	 * there. No IPIs involved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	__raw_writel(__pa_symbol(secondary_startup), SW_BRANCH_VIRT_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static void mmp3_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	scu_enable(SCU_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const struct smp_operations mmp3_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	.smp_prepare_cpus	= mmp3_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	.smp_boot_secondary	= mmp3_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) CPU_METHOD_OF_DECLARE(mmp3_smp, "marvell,mmp3-smp", &mmp3_smp_ops);