^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-mmp/mmp2.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * code name MMP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk/mmp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irqchip/mmp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/hardware/cache-tauros2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "addr-map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "regs-apbc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/soc/mmp/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "mfp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "mmp2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "pm-mmp2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static struct mfp_addr_map mmp2_addr_map[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MFP_ADDR_X(GPIO0, GPIO58, 0x54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MFP_ADDR_X(GPIO59, GPIO73, 0x280),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MFP_ADDR_X(GPIO74, GPIO101, 0x170),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MFP_ADDR(GPIO102, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MFP_ADDR(GPIO103, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MFP_ADDR(GPIO104, 0x1fc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MFP_ADDR(GPIO105, 0x1f8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MFP_ADDR(GPIO106, 0x1f4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MFP_ADDR(GPIO107, 0x1f0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MFP_ADDR(GPIO108, 0x21c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MFP_ADDR(GPIO109, 0x218),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MFP_ADDR(GPIO110, 0x214),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MFP_ADDR(GPIO111, 0x200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MFP_ADDR(GPIO112, 0x244),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MFP_ADDR(GPIO113, 0x25c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MFP_ADDR(GPIO114, 0x164),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MFP_ADDR_X(GPIO115, GPIO122, 0x260),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MFP_ADDR(GPIO123, 0x148),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MFP_ADDR_X(GPIO124, GPIO141, 0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MFP_ADDR(GPIO142, 0x8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MFP_ADDR_X(GPIO143, GPIO151, 0x220),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MFP_ADDR_X(GPIO152, GPIO153, 0x248),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MFP_ADDR_X(GPIO154, GPIO155, 0x254),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MFP_ADDR_X(GPIO156, GPIO159, 0x14c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MFP_ADDR(GPIO160, 0x250),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MFP_ADDR(GPIO161, 0x210),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MFP_ADDR(GPIO162, 0x20c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MFP_ADDR(GPIO163, 0x208),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MFP_ADDR(GPIO164, 0x204),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MFP_ADDR(GPIO165, 0x1ec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MFP_ADDR(GPIO166, 0x1e8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MFP_ADDR(GPIO167, 0x1e4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MFP_ADDR(GPIO168, 0x1e0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MFP_ADDR(PMIC_INT, 0x2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MFP_ADDR(CLK_REQ, 0x160),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MFP_ADDR_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void mmp2_clear_pmic_int(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __iomem *mfpr_pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) data = __raw_readl(mfpr_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __raw_writel(data | (1 << 6), mfpr_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __raw_writel(data, mfpr_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void __init mmp2_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mmp2_init_icu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) icu_irq_chip.irq_set_wake = mmp2_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int __init mmp2_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (cpu_is_mmp2()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #ifdef CONFIG_CACHE_TAUROS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) tauros2_init(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mfp_init_base(MFPR_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mfp_init_addr(mmp2_addr_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mmp2_clk_init(APB_PHYS_BASE + 0x50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) AXI_PHYS_BASE + 0x82800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) APB_PHYS_BASE + 0x15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) postcore_initcall(mmp2_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define APBC_TIMERS APBC_REG(0x024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void __init mmp2_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long clk_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * enable bus/functional clock, enable 6.5MHz (divider 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * release reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __raw_writel(clk_rst, APBC_TIMERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mmp_timer_init(IRQ_MMP2_TIMER1, 6500000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* on-chip devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct resource mmp2_resource_gpio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .start = 0xd4019000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .end = 0xd4019fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .start = IRQ_MMP2_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .end = IRQ_MMP2_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "gpio_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct platform_device mmp2_device_gpio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .name = "mmp2-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .num_resources = ARRAY_SIZE(mmp2_resource_gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .resource = mmp2_resource_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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