Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __ASM_MACH_IRQS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __ASM_MACH_IRQS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Interrupt numbers for PXA168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define IRQ_PXA168_NONE			(-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define IRQ_PXA168_SSP4			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define IRQ_PXA168_SSP3			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define IRQ_PXA168_SSP2			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define IRQ_PXA168_SSP1			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define IRQ_PXA168_PMIC_INT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define IRQ_PXA168_RTC_INT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define IRQ_PXA168_RTC_ALARM		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define IRQ_PXA168_TWSI0		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IRQ_PXA168_GPU			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define IRQ_PXA168_KEYPAD		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define IRQ_PXA168_ONEWIRE		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IRQ_PXA168_TIMER1		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define IRQ_PXA168_TIMER2		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IRQ_PXA168_TIMER3		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define IRQ_PXA168_CMU			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IRQ_PXA168_SSP5			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IRQ_PXA168_MSP_WAKEUP		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IRQ_PXA168_CF_WAKEUP		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IRQ_PXA168_XD_WAKEUP		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IRQ_PXA168_MFU			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IRQ_PXA168_MSP			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define IRQ_PXA168_CF			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define IRQ_PXA168_XD			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IRQ_PXA168_DDR_INT		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define IRQ_PXA168_UART1		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IRQ_PXA168_UART2		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define IRQ_PXA168_UART3		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define IRQ_PXA168_WDT			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define IRQ_PXA168_MAIN_PMU		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define IRQ_PXA168_FRQ_CHANGE		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IRQ_PXA168_SDH1			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IRQ_PXA168_SDH2			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IRQ_PXA168_LCD			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define IRQ_PXA168_CI			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IRQ_PXA168_USB1			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IRQ_PXA168_NAND			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IRQ_PXA168_HIFI_DMA		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define IRQ_PXA168_DMA_INT0		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define IRQ_PXA168_DMA_INT1		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define IRQ_PXA168_GPIOX		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define IRQ_PXA168_USB2			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IRQ_PXA168_AC97			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define IRQ_PXA168_TWSI1		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define IRQ_PXA168_AP_PMU		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define IRQ_PXA168_SM_INT		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * Interrupt numbers for PXA910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define IRQ_PXA910_NONE			(-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IRQ_PXA910_AIRQ			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IRQ_PXA910_SSP3			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define IRQ_PXA910_SSP2			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define IRQ_PXA910_SSP1			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IRQ_PXA910_PMIC_INT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IRQ_PXA910_RTC_INT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define IRQ_PXA910_RTC_ALARM		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define IRQ_PXA910_TWSI0		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IRQ_PXA910_GPU			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define IRQ_PXA910_KEYPAD		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define IRQ_PXA910_ROTARY		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define IRQ_PXA910_TRACKBALL		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IRQ_PXA910_ONEWIRE		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define IRQ_PXA910_AP1_TIMER1		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define IRQ_PXA910_AP1_TIMER2		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define IRQ_PXA910_AP1_TIMER3		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define IRQ_PXA910_IPC_AP0		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define IRQ_PXA910_IPC_AP1		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define IRQ_PXA910_IPC_AP2		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define IRQ_PXA910_IPC_AP3		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define IRQ_PXA910_IPC_AP4		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define IRQ_PXA910_IPC_CP0		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define IRQ_PXA910_IPC_CP1		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define IRQ_PXA910_IPC_CP2		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define IRQ_PXA910_IPC_CP3		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IRQ_PXA910_IPC_CP4		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define IRQ_PXA910_L2_DDR		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define IRQ_PXA910_UART2		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define IRQ_PXA910_UART3		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define IRQ_PXA910_AP2_TIMER1		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define IRQ_PXA910_AP2_TIMER2		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define IRQ_PXA910_CP2_TIMER1		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define IRQ_PXA910_CP2_TIMER2		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define IRQ_PXA910_CP2_TIMER3		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define IRQ_PXA910_GSSP			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define IRQ_PXA910_CP2_WDT		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define IRQ_PXA910_MAIN_PMU		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define IRQ_PXA910_CP_FREQ_CHG		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define IRQ_PXA910_AP_FREQ_CHG		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define IRQ_PXA910_MMC			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define IRQ_PXA910_AEU			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IRQ_PXA910_LCD			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IRQ_PXA910_CCIC			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IRQ_PXA910_IRE			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IRQ_PXA910_USB1			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IRQ_PXA910_NAND			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IRQ_PXA910_HIFI_DMA		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IRQ_PXA910_DMA_INT0		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IRQ_PXA910_DMA_INT1		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IRQ_PXA910_AP_GPIO		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IRQ_PXA910_AP2_TIMER3		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IRQ_PXA910_USB2			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IRQ_PXA910_TWSI1		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IRQ_PXA910_CP_GPIO		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IRQ_PXA910_UART1		59	/* Slow UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IRQ_PXA910_AP_PMU		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IRQ_PXA910_SM_INT		63	/* from PinMux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * Interrupt numbers for MMP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IRQ_MMP2_NONE			(-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IRQ_MMP2_SSP1			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IRQ_MMP2_SSP2			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IRQ_MMP2_SSPA1			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IRQ_MMP2_SSPA2			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IRQ_MMP2_PMIC_MUX		4	/* PMIC & Charger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IRQ_MMP2_RTC_MUX		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IRQ_MMP2_TWSI1			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IRQ_MMP2_GPU			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IRQ_MMP2_KEYPAD_MUX		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IRQ_MMP2_ROTARY			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IRQ_MMP2_TRACKBALL		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IRQ_MMP2_ONEWIRE		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IRQ_MMP2_TIMER1			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IRQ_MMP2_TIMER2			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IRQ_MMP2_TIMER3			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IRQ_MMP2_RIPC			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IRQ_MMP2_TWSI_MUX		17	/* TWSI2 ~ TWSI6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IRQ_MMP2_HDMI			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IRQ_MMP2_SSP3			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IRQ_MMP2_SSP4			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IRQ_MMP2_USB_HS1		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IRQ_MMP2_USB_HS2		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IRQ_MMP2_UART3			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IRQ_MMP2_UART1			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IRQ_MMP2_UART2			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IRQ_MMP2_MIPI_DSI		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IRQ_MMP2_CI2			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IRQ_MMP2_PMU_TIMER1		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IRQ_MMP2_PMU_TIMER2		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IRQ_MMP2_PMU_TIMER3		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IRQ_MMP2_USB_FS			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IRQ_MMP2_MISC_MUX		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IRQ_MMP2_WDT1			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IRQ_MMP2_NAND_DMA		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IRQ_MMP2_USIM			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IRQ_MMP2_MMC			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IRQ_MMP2_WTM			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IRQ_MMP2_LCD			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IRQ_MMP2_CI			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IRQ_MMP2_IRE			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IRQ_MMP2_USB_OTG		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IRQ_MMP2_NAND			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IRQ_MMP2_UART4			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IRQ_MMP2_DMA_FIQ		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IRQ_MMP2_DMA_RIQ		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IRQ_MMP2_GPIO			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IRQ_MMP2_MIPI_HSI1_MUX		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IRQ_MMP2_MMC2			52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IRQ_MMP2_MMC3			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IRQ_MMP2_MMC4			54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IRQ_MMP2_MIPI_HSI0_MUX		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IRQ_MMP2_MSP			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IRQ_MMP2_MIPI_SLIM_DMA		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IRQ_MMP2_PJ4_FREQ_CHG		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IRQ_MMP2_MIPI_SLIM		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IRQ_MMP2_SM			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IRQ_MMP2_MUX_BASE		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* secondary interrupt of INT #4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IRQ_MMP2_PMIC_BASE		(IRQ_MMP2_MUX_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IRQ_MMP2_CHARGER		(IRQ_MMP2_PMIC_BASE + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IRQ_MMP2_PMIC			(IRQ_MMP2_PMIC_BASE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* secondary interrupt of INT #5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IRQ_MMP2_RTC_BASE		(IRQ_MMP2_PMIC_BASE + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IRQ_MMP2_RTC_ALARM		(IRQ_MMP2_RTC_BASE + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IRQ_MMP2_RTC			(IRQ_MMP2_RTC_BASE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* secondary interrupt of INT #9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IRQ_MMP2_KEYPAD_BASE		(IRQ_MMP2_RTC_BASE + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IRQ_MMP2_KPC			(IRQ_MMP2_KEYPAD_BASE + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IRQ_MMP2_ROTORY			(IRQ_MMP2_KEYPAD_BASE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IRQ_MMP2_TBALL			(IRQ_MMP2_KEYPAD_BASE + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* secondary interrupt of INT #17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IRQ_MMP2_TWSI_BASE		(IRQ_MMP2_KEYPAD_BASE + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IRQ_MMP2_TWSI2			(IRQ_MMP2_TWSI_BASE + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IRQ_MMP2_TWSI3			(IRQ_MMP2_TWSI_BASE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IRQ_MMP2_TWSI4			(IRQ_MMP2_TWSI_BASE + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IRQ_MMP2_TWSI5			(IRQ_MMP2_TWSI_BASE + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IRQ_MMP2_TWSI6			(IRQ_MMP2_TWSI_BASE + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* secondary interrupt of INT #35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IRQ_MMP2_MISC_BASE		(IRQ_MMP2_TWSI_BASE + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IRQ_MMP2_PERF			(IRQ_MMP2_MISC_BASE + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IRQ_MMP2_L2_PA_ECC		(IRQ_MMP2_MISC_BASE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IRQ_MMP2_L2_ECC			(IRQ_MMP2_MISC_BASE + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IRQ_MMP2_L2_UECC		(IRQ_MMP2_MISC_BASE + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IRQ_MMP2_DDR			(IRQ_MMP2_MISC_BASE + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IRQ_MMP2_FAB0_TIMEOUT		(IRQ_MMP2_MISC_BASE + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IRQ_MMP2_FAB1_TIMEOUT		(IRQ_MMP2_MISC_BASE + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IRQ_MMP2_FAB2_TIMEOUT		(IRQ_MMP2_MISC_BASE + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IRQ_MMP2_THERMAL		(IRQ_MMP2_MISC_BASE + 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IRQ_MMP2_MAIN_PMU		(IRQ_MMP2_MISC_BASE + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IRQ_MMP2_WDT2			(IRQ_MMP2_MISC_BASE + 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IRQ_MMP2_CORESIGHT		(IRQ_MMP2_MISC_BASE + 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IRQ_MMP2_COMMTX			(IRQ_MMP2_MISC_BASE + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IRQ_MMP2_COMMRX			(IRQ_MMP2_MISC_BASE + 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* secondary interrupt of INT #51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IRQ_MMP2_MIPI_HSI1_BASE		(IRQ_MMP2_MISC_BASE + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IRQ_MMP2_HSI1_CAWAKE		(IRQ_MMP2_MIPI_HSI1_BASE + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IRQ_MMP2_MIPI_HSI_INT1		(IRQ_MMP2_MIPI_HSI1_BASE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* secondary interrupt of INT #55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IRQ_MMP2_MIPI_HSI0_BASE		(IRQ_MMP2_MIPI_HSI1_BASE + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IRQ_MMP2_HSI0_CAWAKE		(IRQ_MMP2_MIPI_HSI0_BASE + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IRQ_MMP2_MIPI_HSI_INT0		(IRQ_MMP2_MIPI_HSI0_BASE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IRQ_MMP2_MUX_END		(IRQ_MMP2_MIPI_HSI0_BASE + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IRQ_GPIO_START			128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MMP_NR_BUILTIN_GPIO		192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MMP_GPIO_TO_IRQ(gpio)		(IRQ_GPIO_START + (gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IRQ_BOARD_START			(IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MMP_NR_IRQS			IRQ_BOARD_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #endif /* __ASM_MACH_IRQS_H */