^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-mmp/devices.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/soc/mmp/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "regs-usb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) int __init pxa_register_device(struct pxa_device_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) void *data, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct resource res[2 + MAX_RESOURCE_DMA];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int i, ret = 0, nres = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) pdev = platform_device_alloc(desc->drv_name, desc->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) if (pdev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) memset(res, 0, sizeof(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (desc->start != -1ul && desc->size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) res[nres].start = desc->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) res[nres].end = desc->start + desc->size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) res[nres].flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) nres++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (desc->irq != NO_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) res[nres].start = desc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) res[nres].end = desc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) res[nres].flags = IORESOURCE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) nres++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) for (i = 0; i < MAX_RESOURCE_DMA; i++, nres++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (desc->dma[i] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) res[nres].start = desc->dma[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) res[nres].end = desc->dma[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) res[nres].flags = IORESOURCE_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ret = platform_device_add_resources(pdev, res, nres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (data && size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ret = platform_device_add_data(pdev, data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return platform_device_add(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #if IS_ENABLED(CONFIG_USB) || IS_ENABLED(CONFIG_USB_GADGET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #if IS_ENABLED(CONFIG_USB_MV_UDC) || IS_ENABLED(CONFIG_USB_EHCI_MV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #if IS_ENABLED(CONFIG_CPU_PXA910) || IS_ENABLED(CONFIG_CPU_PXA168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * The registers read/write routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static unsigned int u2o_get(void __iomem *base, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return readl_relaxed(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void u2o_set(void __iomem *base, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) reg = readl_relaxed(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) reg |= value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writel_relaxed(reg, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) readl_relaxed(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void u2o_clear(void __iomem *base, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reg = readl_relaxed(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg &= ~value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) writel_relaxed(reg, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) readl_relaxed(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void u2o_write(void __iomem *base, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) writel_relaxed(value, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) readl_relaxed(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static DEFINE_MUTEX(phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int phy_init_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int usb_phy_init_internal(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int loops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pr_info("Init usb phy!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Initialize the USB PHY power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (cpu_is_pxa910()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u2o_set(base, UTMI_CTRL, (1<<UTMI_CTRL_INPKT_DELAY_SOF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) | (1<<UTMI_CTRL_PU_REF_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* UTMI_PLL settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) | UTMI_PLL_PLLVDD12_MASK | UTMI_PLL_PLLCALI12_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) | UTMI_PLL_FBDIV_MASK | UTMI_PLL_REFDIV_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) | UTMI_PLL_ICP_MASK | UTMI_PLL_KVCO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u2o_set(base, UTMI_PLL, 0xee<<UTMI_PLL_FBDIV_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) | 0xb<<UTMI_PLL_REFDIV_SHIFT | 3<<UTMI_PLL_PLLVDD18_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) | 3<<UTMI_PLL_PLLVDD12_SHIFT | 3<<UTMI_PLL_PLLCALI12_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) | 1<<UTMI_PLL_ICP_SHIFT | 3<<UTMI_PLL_KVCO_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* UTMI_TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) | UTMI_TX_TXVDD12_MASK | UTMI_TX_CK60_PHSEL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) | UTMI_TX_IMPCAL_VTH_MASK | UTMI_TX_REG_EXT_FS_RCAL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) | UTMI_TX_AMP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u2o_set(base, UTMI_TX, 3<<UTMI_TX_TXVDD12_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) | 4<<UTMI_TX_CK60_PHSEL_SHIFT | 4<<UTMI_TX_IMPCAL_VTH_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) | 8<<UTMI_TX_REG_EXT_FS_RCAL_SHIFT | 3<<UTMI_TX_AMP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* UTMI_RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) | UTMI_REG_SQ_LENGTH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u2o_set(base, UTMI_RX, 7<<UTMI_RX_SQ_THRESH_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) | 2<<UTMI_REG_SQ_LENGTH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* UTMI_IVREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (cpu_is_pxa168())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* fixing Microsoft Altair board interface with NEC hub issue -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Set UTMI_IVREF from 0x4a3 to 0x4bf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u2o_write(base, UTMI_IVREF, 0x4bf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* toggle VCOCAL_START bit of UTMI_PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u2o_set(base, UTMI_PLL, VCOCAL_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) udelay(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u2o_clear(base, UTMI_PLL, VCOCAL_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* toggle REG_RCAL_START bit of UTMI_TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) udelay(400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u2o_set(base, UTMI_TX, REG_RCAL_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) udelay(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u2o_clear(base, UTMI_TX, REG_RCAL_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) udelay(400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Make sure PHY PLL is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) loops = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) loops++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (loops > 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) printk(KERN_WARNING "calibrate timeout, UTMI_PLL %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u2o_get(base, UTMI_PLL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (cpu_is_pxa168()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u2o_set(base, UTMI_RESERVE, 1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Turn on UTMI PHY OTG extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u2o_write(base, UTMI_OTG_ADDON, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int usb_phy_deinit_internal(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pr_info("Deinit usb phy!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (cpu_is_pxa168())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int pxa_usb_phy_init(void __iomem *phy_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mutex_lock(&phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (phy_init_cnt++ == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) usb_phy_init_internal(phy_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mutex_unlock(&phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void pxa_usb_phy_deinit(void __iomem *phy_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) WARN_ON(phy_init_cnt == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mutex_lock(&phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (--phy_init_cnt == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) usb_phy_deinit_internal(phy_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mutex_unlock(&phy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #if IS_ENABLED(CONFIG_USB_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static u64 __maybe_unused usb_dma_mask = ~(u32)0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #if IS_ENABLED(CONFIG_PHY_PXA_USB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct resource pxa168_usb_phy_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .start = PXA168_U2O_PHYBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct platform_device pxa168_device_usb_phy = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .name = "pxa-usb-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .resource = pxa168_usb_phy_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .num_resources = ARRAY_SIZE(pxa168_usb_phy_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .dma_mask = &usb_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .coherent_dma_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #endif /* CONFIG_PHY_PXA_USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #if IS_ENABLED(CONFIG_USB_MV_UDC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct resource pxa168_u2o_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* regbase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .start = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .end = PXA168_U2O_REGBASE + USB_REG_RANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .name = "capregs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* phybase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .start = PXA168_U2O_PHYBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .name = "phyregs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .start = IRQ_PXA168_USB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .end = IRQ_PXA168_USB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct platform_device pxa168_device_u2o = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .name = "mv-udc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .resource = pxa168_u2o_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .num_resources = ARRAY_SIZE(pxa168_u2o_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .dma_mask = &usb_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .coherent_dma_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #endif /* CONFIG_USB_MV_UDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #if IS_ENABLED(CONFIG_USB_EHCI_MV_U2O)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct resource pxa168_u2oehci_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .start = PXA168_U2O_REGBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .end = PXA168_U2O_REGBASE + USB_REG_RANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .start = IRQ_PXA168_USB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .end = IRQ_PXA168_USB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct platform_device pxa168_device_u2oehci = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .name = "pxa-u2oehci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .dma_mask = &usb_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .coherent_dma_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .num_resources = ARRAY_SIZE(pxa168_u2oehci_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .resource = pxa168_u2oehci_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #if IS_ENABLED(CONFIG_USB_MV_OTG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct resource pxa168_u2ootg_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* regbase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .start = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .end = PXA168_U2O_REGBASE + USB_REG_RANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .name = "capregs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* phybase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .start = PXA168_U2O_PHYBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .name = "phyregs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .start = IRQ_PXA168_USB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .end = IRQ_PXA168_USB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct platform_device pxa168_device_u2ootg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .name = "mv-otg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .dma_mask = &usb_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .coherent_dma_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .num_resources = ARRAY_SIZE(pxa168_u2ootg_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .resource = pxa168_u2ootg_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #endif /* CONFIG_USB_MV_OTG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags