Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *   Common address map definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __ASM_MACH_ADDR_MAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __ASM_MACH_ADDR_MAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* APB - Application Subsystem Peripheral Bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * NOTE: the DMA controller registers are actually on the AXI fabric #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * slave port to AHB/APB bridge, due to its close relationship to those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * peripherals on APB, let's count it into the ABP mapping area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define APB_PHYS_BASE		0xd4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define APB_VIRT_BASE		IOMEM(0xfe000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define APB_PHYS_SIZE		0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AXI_PHYS_BASE		0xd4200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AXI_VIRT_BASE		IOMEM(0xfe200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AXI_PHYS_SIZE		0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PGU_PHYS_BASE		0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PGU_VIRT_BASE		IOMEM(0xfe400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PGU_PHYS_SIZE		0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Static Memory Controller - Chip Select 0 and 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SMC_CS0_PHYS_BASE	0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SMC_CS0_PHYS_SIZE	0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SMC_CS1_PHYS_BASE	0x90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SMC_CS1_PHYS_SIZE	0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define APMU_VIRT_BASE		(AXI_VIRT_BASE + 0x82800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define APMU_REG(x)		(APMU_VIRT_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define APBC_VIRT_BASE		(APB_VIRT_BASE + 0x015000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define APBC_REG(x)		(APBC_VIRT_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MPMU_VIRT_BASE		(APB_VIRT_BASE + 0x50000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MPMU_REG(x)		(MPMU_VIRT_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CIU_VIRT_BASE		(AXI_VIRT_BASE + 0x82c00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CIU_REG(x)		(CIU_VIRT_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SCU_VIRT_BASE		(PGU_VIRT_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SCU_REG(x)		(SCU_VIRT_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif /* __ASM_MACH_ADDR_MAP_H */