^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-mediatek/platsmp.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Mediatek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Shunli Wang <shunli.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Yingjoe Chen <yingjoe.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MTK_MAX_CPU 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MTK_SMP_REG_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct mtk_smp_boot_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned long smp_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned int jump_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned int core_keys[MTK_MAX_CPU - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int core_regs[MTK_MAX_CPU - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct mtk_smp_boot_info mtk_mt8135_tz_boot = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 0x80002000, 0x3fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { 0x534c4131, 0x4c415332, 0x41534c33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { 0x3f8, 0x3f8, 0x3f8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct mtk_smp_boot_info mtk_mt6589_boot = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 0x10002000, 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { 0x534c4131, 0x4c415332, 0x41534c33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { 0x38, 0x3c, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct mtk_smp_boot_info mtk_mt7623_boot = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 0x10202000, 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { 0x534c4131, 0x4c415332, 0x41534c33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { 0x38, 0x3c, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { .compatible = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { .compatible = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { .compatible = "mediatek,mt2701", .data = &mtk_mt8135_tz_boot },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { .compatible = "mediatek,mt6589", .data = &mtk_mt6589_boot },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { .compatible = "mediatek,mt7623", .data = &mtk_mt7623_boot },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { .compatible = "mediatek,mt7629", .data = &mtk_mt7623_boot },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void __iomem *mtk_smp_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct mtk_smp_boot_info *mtk_smp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int mtk_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (!mtk_smp_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (!mtk_smp_info->core_keys[cpu-1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) writel_relaxed(mtk_smp_info->core_keys[cpu-1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mtk_smp_base + mtk_smp_info->core_regs[cpu-1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) arch_send_wakeup_ipi_mask(cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static void __init __mtk_smp_prepare_cpus(unsigned int max_cpus, int trustzone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int i, num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const struct of_device_id *infos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (trustzone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) num = ARRAY_SIZE(mtk_tz_smp_boot_infos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) infos = mtk_tz_smp_boot_infos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) num = ARRAY_SIZE(mtk_smp_boot_infos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) infos = mtk_smp_boot_infos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Find smp boot info for this SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (of_machine_is_compatible(infos[i].compatible)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mtk_smp_info = infos[i].data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!mtk_smp_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pr_err("%s: Device is not supported\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (trustzone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* smp_base(trustzone-bootinfo) is reserved by device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mtk_smp_base = phys_to_virt(mtk_smp_info->smp_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mtk_smp_base = ioremap(mtk_smp_info->smp_base, MTK_SMP_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (!mtk_smp_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_err("%s: Can't remap %lx\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mtk_smp_info->smp_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * write the address of slave startup address into the system-wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * jump register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) writel_relaxed(__pa_symbol(secondary_startup_arm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mtk_smp_base + mtk_smp_info->jump_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void __init mtk_tz_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __mtk_smp_prepare_cpus(max_cpus, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void __init mtk_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __mtk_smp_prepare_cpus(max_cpus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct smp_operations mt81xx_tz_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .smp_prepare_cpus = mtk_tz_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .smp_boot_secondary = mtk_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CPU_METHOD_OF_DECLARE(mt81xx_tz_smp, "mediatek,mt81xx-tz-smp", &mt81xx_tz_smp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct smp_operations mt6589_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .smp_prepare_cpus = mtk_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .smp_boot_secondary = mtk_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CPU_METHOD_OF_DECLARE(mt6589_smp, "mediatek,mt6589-smp", &mt6589_smp_ops);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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