Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Device Tree support for Mediatek SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2014 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: Matthias Brugger <matthias.bgg@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GPT6_CON_MT65xx 0x10008060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GPT_ENABLE      0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static void __init mediatek_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	void __iomem *gpt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	if (of_machine_is_compatible("mediatek,mt6589") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	    of_machine_is_compatible("mediatek,mt7623") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	    of_machine_is_compatible("mediatek,mt8135") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	    of_machine_is_compatible("mediatek,mt8127")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		/* turn on GPT6 which ungates arch timer clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		gpt_base = ioremap(GPT6_CON_MT65xx, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		/* enable clock and set to free-run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		writel(GPT_ENABLE, gpt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		iounmap(gpt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	of_clk_init(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	timer_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const char * const mediatek_board_dt_compat[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	"mediatek,mt2701",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	"mediatek,mt6589",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	"mediatek,mt6592",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	"mediatek,mt7623",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	"mediatek,mt7629",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	"mediatek,mt8127",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	"mediatek,mt8135",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	.dt_compat	= mediatek_board_dt_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	.init_time	= mediatek_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MACHINE_END