^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-lpc32xx/pm.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Modified by Kevin Wells <kevin.wells@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 2005 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * LPC32XX CPU and system power management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * The LPC32XX has three CPU modes for controlling system power: run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * direct-run, and halt modes. When switching between halt and run modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * the CPU transistions through direct-run mode. For Linux, direct-run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * mode is not used in normal operation. Halt mode is used when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * system is fully suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Run mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * the HCLK_PLL rate. Linux runs in this mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Direct-run mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * source or the frequency of the main oscillator. In this mode, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * HCLK_PLL can be safely enabled, changed, or disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Halt mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * SYSCLK is gated off and the CPU and system clocks are halted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * key scanner, etc.) still operate if enabled. In this state, an enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * system event (ie, GPIO state change, RTC match, key press, etc.) will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * wake the system up back into direct-run mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * DRAM refresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * DRAM clocking and refresh are slightly different for systems with DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * SDRAM will still be accessible in direct-run mode. In DDR based systems,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * a transition to direct-run mode will stop all DDR accesses (no clocks).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Because of this, the code to switch power modes and the code to enter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * and exit DRAM self-refresh modes must not be executed in DRAM. A small
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * section of IRAM is used instead for this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Suspend is handled with the following logic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Backup a small area of IRAM used for the suspend code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Copy suspend code to IRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Transfer control to code in IRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Places DRAMs in self-refresh mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Enter direct-run mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Save state of HCLK_PLL PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Disable HCLK_PLL PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Enter halt mode - CPU and buses will stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * System enters direct-run mode when an enabled event occurs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * HCLK PLL state is restored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Run mode is entered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * DRAMS are placed back into normal mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Code execution returns from IRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * IRAM code are used for suspend is restored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Suspend mode is exited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include "lpc32xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Both STANDBY and MEM suspend states are handled the same with no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * loss of CPU or memory state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int lpc32xx_pm_enter(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int (*lpc32xx_suspend_ptr) (void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void *iram_swap_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Allocate some space for temporary IRAM storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) iram_swap_area = kmemdup((void *)TEMP_IRAM_AREA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) lpc32xx_sys_suspend_sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!iram_swap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Copy code to suspend system into IRAM. The suspend code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * needs to run from IRAM as DRAM may no longer be available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * when the PLL is stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) lpc32xx_sys_suspend_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) flush_icache_range((unsigned long)TEMP_IRAM_AREA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Transfer to suspend code in IRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) (void) lpc32xx_suspend_ptr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Restore original IRAM contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) lpc32xx_sys_suspend_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) kfree(iram_swap_area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct platform_suspend_ops lpc32xx_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .valid = suspend_valid_only_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .enter = lpc32xx_pm_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define EMC_DYN_MEM_CTRL_OFS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define EMC_SRMMC (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int __init lpc32xx_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Setup SDRAM self-refresh clock to automatically disable o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * start of self-refresh. This only needs to be done once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) suspend_set_ops(&lpc32xx_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) arch_initcall(lpc32xx_pm_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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