Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Platform support for LPC32xx SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: Kevin Wells <kevin.wells@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 2010 NXP Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/amba/pl08x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mtd/lpc32xx_mlc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mtd/lpc32xx_slc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static struct pl08x_channel_data pl08x_slave_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		.bus_id = "nand-slc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		.min_signal = 1, /* SLC NAND Flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		.max_signal = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		.periph_buses = PL08X_AHB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		.bus_id = "nand-mlc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		.min_signal = 12, /* MLC NAND Flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		.max_signal = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		.periph_buses = PL08X_AHB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int pl08x_get_signal(const struct pl08x_channel_data *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	return cd->min_signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct pl08x_platform_data pl08x_pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	/* Some reasonable memcpy defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	.memcpy_burst_size = PL08X_BURST_SZ_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	.memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	.slave_channels = &pl08x_slave_channels[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	.num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	.get_xfer_signal = pl08x_get_signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	.put_xfer_signal = pl08x_put_signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	.lli_buses = PL08X_AHB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	.mem_buses = PL08X_AHB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	.dma_filter = pl08x_filter_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	.dma_filter = pl08x_filter_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		       &lpc32xx_slc_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		       &lpc32xx_mlc_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void __init lpc3250_machine_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	lpc32xx_serial_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	of_platform_default_populate(NULL, lpc32xx_auxdata_lookup, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const char *const lpc32xx_dt_compat[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	"nxp,lpc3220",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	"nxp,lpc3230",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	"nxp,lpc3240",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	"nxp,lpc3250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	.atag_offset	= 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	.map_io		= lpc32xx_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 	.init_machine	= lpc3250_machine_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 	.dt_compat	= lpc32xx_dt_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MACHINE_END