^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-lpc32xx/include/mach/platform.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Kevin Wells <kevin.wells@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2010 NXP Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __ARM_LPC32XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __ARM_LPC32XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _SBF(f, v) ((v) << (f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define _BIT(n) _SBF(n, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * AHB 0 physical base addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LPC32XX_SLC_BASE 0x20020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LPC32XX_SSP0_BASE 0x20084000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LPC32XX_SPI1_BASE 0x20088000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LPC32XX_SSP1_BASE 0x2008C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LPC32XX_SPI2_BASE 0x20090000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LPC32XX_I2S0_BASE 0x20094000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LPC32XX_SD_BASE 0x20098000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LPC32XX_I2S1_BASE 0x2009C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LPC32XX_MLC_BASE 0x200A8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LPC32XX_AHB0_START LPC32XX_SLC_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LPC32XX_AHB0_SIZE 0x00089000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * AHB 1 physical base addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LPC32XX_DMA_BASE 0x31000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LPC32XX_USB_BASE 0x31020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPC32XX_USBH_BASE 0x31020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPC32XX_USB_OTG_BASE 0x31020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LPC32XX_OTG_I2C_BASE 0x31020300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LPC32XX_LCD_BASE 0x31040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LPC32XX_ETHERNET_BASE 0x31060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LPC32XX_EMC_BASE 0x31080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LPC32XX_ETB_CFG_BASE 0x310C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPC32XX_ETB_DATA_BASE 0x310E0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LPC32XX_AHB1_START LPC32XX_DMA_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LPC32XX_AHB1_SIZE 0x000E1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * FAB physical base addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LPC32XX_CLK_PM_BASE 0x40004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LPC32XX_MIC_BASE 0x40008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LPC32XX_SIC1_BASE 0x4000C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LPC32XX_SIC2_BASE 0x40010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LPC32XX_HS_UART1_BASE 0x40014000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LPC32XX_HS_UART2_BASE 0x40018000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LPC32XX_HS_UART7_BASE 0x4001C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LPC32XX_RTC_BASE 0x40024000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LPC32XX_RTC_RAM_BASE 0x40024080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LPC32XX_GPIO_BASE 0x40028000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LPC32XX_PWM3_BASE 0x4002C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LPC32XX_PWM4_BASE 0x40030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LPC32XX_MSTIM_BASE 0x40034000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LPC32XX_HSTIM_BASE 0x40038000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LPC32XX_WDTIM_BASE 0x4003C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LPC32XX_DEBUG_CTRL_BASE 0x40040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LPC32XX_TIMER0_BASE 0x40044000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LPC32XX_ADC_BASE 0x40048000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LPC32XX_TIMER1_BASE 0x4004C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LPC32XX_KSCAN_BASE 0x40050000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LPC32XX_UART_CTRL_BASE 0x40054000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LPC32XX_TIMER2_BASE 0x40058000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LPC32XX_PWM1_BASE 0x4005C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LPC32XX_PWM2_BASE 0x4005C004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LPC32XX_TIMER3_BASE 0x40060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * APB physical base addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LPC32XX_UART3_BASE 0x40080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LPC32XX_UART4_BASE 0x40088000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LPC32XX_UART5_BASE 0x40090000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LPC32XX_UART6_BASE 0x40098000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LPC32XX_I2C1_BASE 0x400A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LPC32XX_I2C2_BASE 0x400A8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * FAB and APB base and sizing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LPC32XX_FABAPB_START LPC32XX_CLK_PM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LPC32XX_FABAPB_SIZE 0x000A5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Internal memory bases and sizes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define LPC32XX_IRAM_BASE 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LPC32XX_IROM_BASE 0x0C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * External Static Memory Bank Address Space Bases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LPC32XX_EMC_CS0_BASE 0xE0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LPC32XX_EMC_CS1_BASE 0xE1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LPC32XX_EMC_CS2_BASE 0xE2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LPC32XX_EMC_CS3_BASE 0xE3000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * External SDRAM Memory Bank Address Space Bases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LPC32XX_EMC_DYCS0_BASE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define LPC32XX_EMC_DYCS1_BASE 0xA0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Clock and crystal information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LPC32XX_MAIN_OSC_FREQ 13000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LPC32XX_CLOCK_OSC_FREQ 32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Clock and Power control register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LPC32XX_CLKPWR_DEBUG_CTRL _PMREG(0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LPC32XX_CLKPWR_BOOTMAP _PMREG(0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LPC32XX_CLKPWR_P01_ER _PMREG(0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LPC32XX_CLKPWR_USBCLK_PDIV _PMREG(0x01C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LPC32XX_CLKPWR_INT_ER _PMREG(0x020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LPC32XX_CLKPWR_INT_RS _PMREG(0x024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LPC32XX_CLKPWR_INT_SR _PMREG(0x028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LPC32XX_CLKPWR_INT_AP _PMREG(0x02C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define LPC32XX_CLKPWR_PIN_ER _PMREG(0x030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LPC32XX_CLKPWR_PIN_RS _PMREG(0x034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LPC32XX_CLKPWR_PIN_SR _PMREG(0x038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LPC32XX_CLKPWR_PIN_AP _PMREG(0x03C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LPC32XX_CLKPWR_HCLK_DIV _PMREG(0x040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LPC32XX_CLKPWR_PWR_CTRL _PMREG(0x044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define LPC32XX_CLKPWR_PLL397_CTRL _PMREG(0x048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define LPC32XX_CLKPWR_MAIN_OSC_CTRL _PMREG(0x04C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define LPC32XX_CLKPWR_SYSCLK_CTRL _PMREG(0x050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LPC32XX_CLKPWR_LCDCLK_CTRL _PMREG(0x054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LPC32XX_CLKPWR_HCLKPLL_CTRL _PMREG(0x058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 _PMREG(0x060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LPC32XX_CLKPWR_USB_CTRL _PMREG(0x064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LPC32XX_CLKPWR_SDRAMCLK_CTRL _PMREG(0x068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LPC32XX_CLKPWR_DDR_LAP_NOM _PMREG(0x06C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LPC32XX_CLKPWR_DDR_LAP_COUNT _PMREG(0x070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LPC32XX_CLKPWR_DDR_LAP_DELAY _PMREG(0x074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define LPC32XX_CLKPWR_SSP_CLK_CTRL _PMREG(0x078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define LPC32XX_CLKPWR_I2S_CLK_CTRL _PMREG(0x07C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LPC32XX_CLKPWR_MS_CTRL _PMREG(0x080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define LPC32XX_CLKPWR_MACCLK_CTRL _PMREG(0x090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LPC32XX_CLKPWR_TEST_CLK_SEL _PMREG(0x0A4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define LPC32XX_CLKPWR_SFW_INT _PMREG(0x0A8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define LPC32XX_CLKPWR_I2C_CLK_CTRL _PMREG(0x0AC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define LPC32XX_CLKPWR_KEY_CLK_CTRL _PMREG(0x0B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define LPC32XX_CLKPWR_ADC_CLK_CTRL _PMREG(0x0B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define LPC32XX_CLKPWR_PWM_CLK_CTRL _PMREG(0x0B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define LPC32XX_CLKPWR_TIMER_CLK_CTRL _PMREG(0x0BC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 _PMREG(0x0C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define LPC32XX_CLKPWR_SPI_CLK_CTRL _PMREG(0x0C4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define LPC32XX_CLKPWR_NAND_CLK_CTRL _PMREG(0x0C8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define LPC32XX_CLKPWR_UART3_CLK_CTRL _PMREG(0x0D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LPC32XX_CLKPWR_UART4_CLK_CTRL _PMREG(0x0D4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define LPC32XX_CLKPWR_UART5_CLK_CTRL _PMREG(0x0D8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define LPC32XX_CLKPWR_UART6_CLK_CTRL _PMREG(0x0DC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define LPC32XX_CLKPWR_IRDA_CLK_CTRL _PMREG(0x0E0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define LPC32XX_CLKPWR_UART_CLK_CTRL _PMREG(0x0E4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define LPC32XX_CLKPWR_DMA_CLK_CTRL _PMREG(0x0E8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define LPC32XX_CLKPWR_AUTOCLOCK _PMREG(0x0EC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define LPC32XX_CLKPWR_DEVID(x) _PMREG(0x130 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * clkpwr_debug_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT _BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * clkpwr_bootmap register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * clkpwr_start_gpio register bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT _BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT _BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT _BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT _BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT _BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT _BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT _BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT _BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT _BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT _BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT _BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT _BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT _BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT _BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT _BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT _BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT _BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT _BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT _BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT _BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT _BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT _BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT _BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT _BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT _BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT _BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT _BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT _BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT _BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT _BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * clkpwr_usbclk_pdiv register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define LPC32XX_CLKPWR_USBPDIV_PLL_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * clkpwr_start_pol_int, register bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define LPC32XX_CLKPWR_INTSRC_ADC_BIT _BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define LPC32XX_CLKPWR_INTSRC_TS_P_BIT _BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT _BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT _BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define LPC32XX_CLKPWR_INTSRC_RTC_BIT _BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT _BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define LPC32XX_CLKPWR_INTSRC_USB_BIT _BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define LPC32XX_CLKPWR_INTSRC_I2C_BIT _BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT _BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT _BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define LPC32XX_CLKPWR_INTSRC_KEY_BIT _BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define LPC32XX_CLKPWR_INTSRC_MAC_BIT _BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define LPC32XX_CLKPWR_INTSRC_P0P1_BIT _BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT _BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT _BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT _BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT _BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * clkpwr_start_pol_pin register bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT _BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT _BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT _BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT _BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT _BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT _BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT _BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT _BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT _BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT _BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT _BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT _BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT _BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT _BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT _BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT _BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT _BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT _BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT _BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT _BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT _BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT _BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT _BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT _BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT _BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * clkpwr_hclk_div register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP (0x0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF (0x2 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n) (((n) & 0x1F) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n) ((n) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * clkpwr_pwr_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define LPC32XX_CLKPWR_CTRL_FORCE_PCLK _BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define LPC32XX_CLKPWR_SDRAM_SELF_RFSH _BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH _BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH _BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT _BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT _BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN _BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define LPC32XX_CLKPWR_SELECT_RUN_MODE _BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define LPC32XX_CLKPWR_STOP_MODE_CTRL _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * clkpwr_pll397_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define LPC32XX_CLKPWR_PLL397_MSLOCK_STS _BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define LPC32XX_CLKPWR_PLL397_BYPASS _BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define LPC32XX_CLKPWR_PLL397_BIAS_NORM 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define LPC32XX_CLKPWR_PLL397_BIAS_N12_5 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define LPC32XX_CLKPWR_PLL397_BIAS_N25 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define LPC32XX_CLKPWR_PLL397_BIAS_N37_5 0x0C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define LPC32XX_CLKPWR_PLL397_BIAS_P12_5 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define LPC32XX_CLKPWR_PLL397_BIAS_P25 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define LPC32XX_CLKPWR_PLL397_BIAS_P37_5 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define LPC32XX_CLKPWR_PLL397_BIAS_P50 0x1C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define LPC32XX_CLKPWR_PLL397_BIAS_MASK 0x1C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * clkpwr_main_osc_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define LPC32XX_CLKPWR_MOSC_ADD_CAP(n) (((n) & 0x7F) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define LPC32XX_CLKPWR_MOSC_CAP_MASK (0x7F << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define LPC32XX_CLKPWR_TEST_MODE _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define LPC32XX_CLKPWR_MOSC_DISABLE _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * clkpwr_sysclk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n) (((n) & 0x3FF) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define LPC32XX_CLKPWR_SYSCTRL_BP_MASK (0x3FF << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define LPC32XX_CLKPWR_SYSCTRL_USEPLL397 _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * clkpwr_lcdclk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24 0x0C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C 0x1C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK 0x01C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define LPC32XX_CLKPWR_LCDCTRL_CLK_EN 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n) ((n - 1) & 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK 0x001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * clkpwr_hclkpll_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define LPC32XX_CLKPWR_HCLKPLL_POWER_UP _BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS _BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS _BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK _BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define LPC32XX_CLKPWR_HCLKPLL_PLLM(n) (((n) & 0xFF) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define LPC32XX_CLKPWR_HCLKPLL_PLL_STS _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * clkpwr_adc_clk_ctrl_1 register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n) (((n) & 0xFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL _BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * clkpwr_usb_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define LPC32XX_CLKPWR_USBCTRL_HCLK_EN _BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN _BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN _BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN _BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define LPC32XX_CLKPWR_USBCTRL_PU_ADD (0x0 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER (0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define LPC32XX_CLKPWR_USBCTRL_PD_ADD (0x3 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define LPC32XX_CLKPWR_USBCTRL_CLK_EN2 _BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define LPC32XX_CLKPWR_USBCTRL_CLK_EN1 _BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP _BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS _BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS _BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK _BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n) (((n) & 0x3) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define LPC32XX_CLKPWR_USBCTRL_PLL_STS _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * clkpwr_sdramclk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK _BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW _BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT _BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET _BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n) (((n) & 0x1F) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS _BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n) (((n) & 0x7) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define LPC32XX_CLKPWR_SDRCLK_USE_CAL _BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define LPC32XX_CLKPWR_SDRCLK_DO_CAL _BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC _BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n) (((n) & 0x1F) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define LPC32XX_CLKPWR_SDRCLK_USE_DDR _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define LPC32XX_CLKPWR_SDRCLK_CLK_DIS _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * clkpwr_ssp_blk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX _BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX _BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX _BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX _BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * clkpwr_i2s_clk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX _BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX _BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA _BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX _BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX _BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * clkpwr_ms_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS _BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN _BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS _BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS _BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS _BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define LPC32XX_CLKPWR_MSCARD_SDCARD_EN _BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n) ((n) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * clkpwr_macclk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define LPC32XX_CLKPWR_MACCTRL_PINS_MSK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN _BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * clkpwr_test_clk_sel register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK (0x0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC (0x2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK (0x3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN _BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK (0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK (0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC (0x5 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397 (0x7 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK (0x7 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * clkpwr_sw_int register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define LPC32XX_CLKPWR_SW_INT(n) (_BIT(0) | (((n) & 0x7F) << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define LPC32XX_CLKPWR_SW_GET_ARG(n) (((n) & 0xFE) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * clkpwr_i2c_clk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE _BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE _BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE _BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * clkpwr_key_clk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * clkpwr_adc_clk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * clkpwr_pwm_clk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n) (((n) & 0xF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n) (((n) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * clkpwr_timer_clk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define LPC32XX_CLKPWR_PWMCLK_WDOG_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * clkpwr_timers_pwms_clk_ctrl_1 register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * clkpwr_spi_clk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define LPC32XX_CLKPWR_SPICLK_USE_SPI2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define LPC32XX_CLKPWR_SPICLK_USE_SPI1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * clkpwr_nand_clk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define LPC32XX_CLKPWR_NANDCLK_DMA_RNB 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define LPC32XX_CLKPWR_NANDCLK_DMA_INT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define LPC32XX_CLKPWR_NANDCLK_SEL_SLC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * and clkpwr_uart6_clk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define LPC32XX_CLKPWR_UART_Y_DIV(y) ((y) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define LPC32XX_CLKPWR_UART_X_DIV(x) (((x) & 0xFF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define LPC32XX_CLKPWR_UART_USE_HCLK _BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * clkpwr_irda_clk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define LPC32XX_CLKPWR_IRDA_Y_DIV(y) ((y) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define LPC32XX_CLKPWR_IRDA_X_DIV(x) (((x) & 0xFF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * clkpwr_uart_clk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN _BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN _BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * clkpwr_dmaclk_ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * clkpwr_autoclock register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define LPC32XX_CLKPWR_AUTOCLK_USB_EN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define LPC32XX_CLKPWR_AUTOCLK_IROM_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * Interrupt controller register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * Timer/counter register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * ir register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * tcr register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define LPC32XX_TIMER_CNTR_TCR_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define LPC32XX_TIMER_CNTR_TCR_RESET 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * mcr register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Standard UART register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define LPC32XX_UART_DLL_FIFO(x) io_p2v((x) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define LPC32XX_UART_DLM_IER(x) io_p2v((x) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define LPC32XX_UART_IIR_FCR(x) io_p2v((x) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define LPC32XX_UART_MODEM_CTRL(x) io_p2v((x) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define LPC32XX_UART_MODEM_STATUS(x) io_p2v((x) + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define LPC32XX_UART_RXLEV(x) io_p2v((x) + 0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * UART control structure offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define _UCREG(x) io_p2v(\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) LPC32XX_UART_CTRL_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define LPC32XX_UARTCTL_CTRL _UCREG(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define LPC32XX_UARTCTL_CLKMODE _UCREG(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define LPC32XX_UARTCTL_CLOOP _UCREG(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * ctrl register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define LPC32XX_UART_U3_MD_CTRL_EN _BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define LPC32XX_UART_IRRX6_INV_EN _BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define LPC32XX_UART_HDPX_EN _BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define LPC32XX_UART_UART6_IRDAMOD_BYPASS _BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define LPC32XX_RT_IRTX6_INV_EN _BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define LPC32XX_RT_IRTX6_INV_MIR_EN _BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define LPC32XX_RT_RX_IRPULSE_3_16_115K _BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define LPC32XX_RT_TX_IRPULSE_3_16_115K _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define LPC32XX_UART_U5_ROUTE_TO_USB _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * clkmode register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define LPC32XX_UART_ENABLED_CLOCKS(n) (((n) >> 16) & 0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define LPC32XX_UART_ENABLED_CLOCK(n, u) (((n) >> (16 + (u))) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define LPC32XX_UART_ENABLED_CLKS_ANY _BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define LPC32XX_UART_CLKMODE_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define LPC32XX_UART_CLKMODE_ON 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define LPC32XX_UART_CLKMODE_AUTO 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define LPC32XX_UART_CLKMODE_MASK(u) (0x3 << ((((u) - 3) * 2) + 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define LPC32XX_UART_CLKMODE_LOAD(m, u) ((m) << ((((u) - 3) * 2) + 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * GPIO Module Register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define _GPREG(x) io_p2v(LPC32XX_GPIO_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define LPC32XX_GPIO_P_MUX_SET _GPREG(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define LPC32XX_GPIO_P_MUX_CLR _GPREG(0x104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define LPC32XX_GPIO_P_MUX_STATE _GPREG(0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define LPC32XX_GPIO_P3_MUX_SET _GPREG(0x110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define LPC32XX_GPIO_P3_MUX_CLR _GPREG(0x114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define LPC32XX_GPIO_P3_MUX_STATE _GPREG(0x118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define LPC32XX_GPIO_P0_MUX_SET _GPREG(0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define LPC32XX_GPIO_P0_MUX_CLR _GPREG(0x124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define LPC32XX_GPIO_P0_MUX_STATE _GPREG(0x128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * USB Otg Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* USB OTG CLK CTRL bit defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * Start of virtual addresses for IO devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define IO_BASE 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) IO_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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