Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * arch/arm/mach-ixp4xx/vulcan-setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Arcom/Eurotech Vulcan board-setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * based on fsg-setup.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *	Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/if_ether.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/w1-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/mtd/plat-ram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/mach/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static struct flash_platform_data vulcan_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	.map_name	= "cfi_probe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	.width		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static struct resource vulcan_flash_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	.flags			= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static struct platform_device vulcan_flash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.name			= "IXP4XX-Flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	.id			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	.dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.platform_data	= &vulcan_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.resource		= &vulcan_flash_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.num_resources		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static struct platdata_mtd_ram vulcan_sram_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.mapname	= "Vulcan SRAM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.bankwidth	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static struct resource vulcan_sram_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.flags			= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static struct platform_device vulcan_sram = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.name			= "mtd-ram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.id			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		.platform_data	= &vulcan_sram_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.resource		= &vulcan_sram_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.num_resources		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static struct resource vulcan_uart_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.start		= IXP4XX_UART1_BASE_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.flags		= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.start		= IXP4XX_UART2_BASE_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.flags		= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.flags		= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static struct plat_serial8250_port vulcan_uart_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		.mapbase	= IXP4XX_UART1_BASE_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.irq		= IRQ_IXP4XX_UART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.iotype		= UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		.regshift	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.uartclk	= IXP4XX_UART_XTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.mapbase	= IXP4XX_UART2_BASE_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		.irq		= IRQ_IXP4XX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.iotype		= UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.regshift	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.uartclk	= IXP4XX_UART_XTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.irq		= IXP4XX_GPIO_IRQ(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.irqflags	= IRQF_TRIGGER_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.flags		= UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.iotype		= UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.uartclk	= 1843200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		.irq		= IXP4XX_GPIO_IRQ(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.irqflags	= IRQF_TRIGGER_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.flags		= UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.iotype		= UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.uartclk	= 1843200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct platform_device vulcan_uart = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.name			= "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.id			= PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.platform_data	= vulcan_uart_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.resource		= vulcan_uart_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.num_resources		= ARRAY_SIZE(vulcan_uart_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct resource vulcan_npeb_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.start		= IXP4XX_EthB_BASE_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.end		= IXP4XX_EthB_BASE_PHYS + 0x0fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		.flags		= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static struct resource vulcan_npec_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.start		= IXP4XX_EthC_BASE_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.end		= IXP4XX_EthC_BASE_PHYS + 0x0fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.flags		= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct eth_plat_info vulcan_plat_eth[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.phy		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		.rxq		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		.txreadyq	= 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.phy		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.rxq		= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.txreadyq	= 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct platform_device vulcan_eth[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		.name			= "ixp4xx_eth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.id			= IXP4XX_ETH_NPEB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		.dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			.platform_data	= &vulcan_plat_eth[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		.num_resources		= ARRAY_SIZE(vulcan_npeb_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.resource		= vulcan_npeb_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.name			= "ixp4xx_eth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.id			= IXP4XX_ETH_NPEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			.platform_data	= &vulcan_plat_eth[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.num_resources		= ARRAY_SIZE(vulcan_npec_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		.resource		= vulcan_npec_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct resource vulcan_max6369_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.flags			= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct platform_device vulcan_max6369 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.name			= "max6369_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.id			= -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.resource		= &vulcan_max6369_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.num_resources		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct gpiod_lookup_table vulcan_w1_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.dev_id = "w1-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", 14, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct w1_gpio_platform_data vulcan_w1_gpio_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* Intentionally left blank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct platform_device vulcan_w1_gpio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.name			= "w1-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.id			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.dev			= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.platform_data	= &vulcan_w1_gpio_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct platform_device *vulcan_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	&vulcan_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	&vulcan_flash,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	&vulcan_sram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	&vulcan_max6369,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	&vulcan_eth[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	&vulcan_eth[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	&vulcan_w1_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void __init vulcan_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ixp4xx_sys_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/* Flash is spread over both CS0 and CS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	vulcan_flash_resource.start	 = IXP4XX_EXP_BUS_BASE(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	vulcan_flash_resource.end	 = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	*IXP4XX_EXP_CS0 = IXP4XX_EXP_BUS_CS_EN		|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			  IXP4XX_EXP_BUS_STROBE_T(3)	|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			  IXP4XX_EXP_BUS_SIZE(0xF)	|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			  IXP4XX_EXP_BUS_BYTE_RD16	|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			  IXP4XX_EXP_BUS_WR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/* SRAM on CS2, (256kB, 8bit, writable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	vulcan_sram_resource.start	= IXP4XX_EXP_BUS_BASE(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	vulcan_sram_resource.end	= IXP4XX_EXP_BUS_BASE(2) + SZ_256K - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	*IXP4XX_EXP_CS2 = IXP4XX_EXP_BUS_CS_EN		|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			  IXP4XX_EXP_BUS_STROBE_T(1)	|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			  IXP4XX_EXP_BUS_HOLD_T(2)	|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			  IXP4XX_EXP_BUS_SIZE(9)	|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			  IXP4XX_EXP_BUS_SPLT_EN	|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			  IXP4XX_EXP_BUS_WR_EN		|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			  IXP4XX_EXP_BUS_BYTE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/* XR16L2551 on CS3 (Moto style, 512 bytes, 8bits, writable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	vulcan_uart_resources[2].start	= IXP4XX_EXP_BUS_BASE(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	vulcan_uart_resources[2].end	= IXP4XX_EXP_BUS_BASE(3) + 16 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	vulcan_uart_data[2].mapbase	= vulcan_uart_resources[2].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	vulcan_uart_data[3].mapbase	= vulcan_uart_data[2].mapbase + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN		|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			  IXP4XX_EXP_BUS_STROBE_T(3)	|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			  IXP4XX_EXP_BUS_CYCLES(IXP4XX_EXP_BUS_CYCLES_MOTOROLA)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			  IXP4XX_EXP_BUS_WR_EN		|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			  IXP4XX_EXP_BUS_BYTE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	/* GPIOS on CS4 (512 bytes, 8bits, writable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	*IXP4XX_EXP_CS4 = IXP4XX_EXP_BUS_CS_EN		|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			  IXP4XX_EXP_BUS_WR_EN		|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			  IXP4XX_EXP_BUS_BYTE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	/* max6369 on CS5 (512 bytes, 8bits, writable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	vulcan_max6369_resource.start	= IXP4XX_EXP_BUS_BASE(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	vulcan_max6369_resource.end	= IXP4XX_EXP_BUS_BASE(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	*IXP4XX_EXP_CS5 = IXP4XX_EXP_BUS_CS_EN		|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			  IXP4XX_EXP_BUS_WR_EN		|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			  IXP4XX_EXP_BUS_BYTE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	gpiod_add_lookup_table(&vulcan_w1_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	platform_add_devices(vulcan_devices, ARRAY_SIZE(vulcan_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	/* Maintainer: Marc Zyngier <maz@misterjones.org> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.map_io		= ixp4xx_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.init_early	= ixp4xx_init_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.init_irq	= ixp4xx_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.init_time	= ixp4xx_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.atag_offset	= 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.init_machine	= vulcan_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #if defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.dma_zone_size	= SZ_64M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.restart	= ixp4xx_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MACHINE_END