Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/arch/mach-ixp4xx/vulcan-pci.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Vulcan board-level PCI initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * based on ixdp425-pci.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *	Copyright (C) 2002 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *	Copyright (C) 2003-2004 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* PCI controller GPIO to IRQ pin mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define INTA	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define INTB	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void __init vulcan_pci_preinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #ifndef CONFIG_IXP4XX_INDIRECT_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	 * Cardbus bridge wants way more than the SoC can actually offer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	 * and leaves the whole PCI bus in a mess. Artificially limit it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	 * to 8MB per region. Of course indirect mode doesn't have this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	 * limitation...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	pci_cardbus_mem_size = SZ_8M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		(int)(pci_cardbus_mem_size >> 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	ixp4xx_pci_preinit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int __init vulcan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	if (slot == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		return IXP4XX_GPIO_IRQ(INTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	if (slot == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		return IXP4XX_GPIO_IRQ(INTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct hw_pci vulcan_pci __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	.nr_controllers	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	.ops		= &ixp4xx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	.preinit	= vulcan_pci_preinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	.setup		= ixp4xx_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	.map_irq	= vulcan_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int __init vulcan_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	if (machine_is_arcom_vulcan())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		pci_common_init(&vulcan_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) subsys_initcall(vulcan_pci_init);