Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/arm/mach-ixp4xx/nas100d-pci.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * NAS 100d board-level PCI initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * based on ixdp425-pci.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *	Copyright (C) 2002 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *	Copyright (C) 2003-2004 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * Maintainer: http://www.nslu2-linux.org/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MAX_DEV		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IRQ_LINES	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* PCI controller GPIO to IRQ pin mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define INTA		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define INTB		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define INTC		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define INTD		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define INTE		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __init nas100d_pci_preinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	ixp4xx_pci_preinit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		{ IXP4XX_GPIO_IRQ(INTA), -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		{ IXP4XX_GPIO_IRQ(INTB), -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		{ IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		  IXP4XX_GPIO_IRQ(INTE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		return pci_irq_table[slot - 1][pin - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct hw_pci __initdata nas100d_pci = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	.nr_controllers = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	.ops		= &ixp4xx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	.preinit	= nas100d_pci_preinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	.setup		= ixp4xx_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	.map_irq	= nas100d_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int __init nas100d_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	if (machine_is_nas100d())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		pci_common_init(&nas100d_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) subsys_initcall(nas100d_pci_init);