Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * arch/arm/mach-ixp4xx/ixdp425-setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * IXDP425/IXCDP1100 board-setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2003-2005 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Author: Deepak Saxena <dsaxena@plexity.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/mtd/platnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <asm/mach/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define IXDP425_SDA_PIN		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define IXDP425_SCL_PIN		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* NAND Flash pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IXDP425_NAND_NCE_PIN	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IXDP425_NAND_CMD_BYTE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IXDP425_NAND_ADDR_BYTE	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static struct flash_platform_data ixdp425_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.map_name	= "cfi_probe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.width		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static struct resource ixdp425_flash_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.flags		= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static struct platform_device ixdp425_flash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.name		= "IXP4XX-Flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.id		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.dev		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		.platform_data = &ixdp425_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.num_resources	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.resource	= &ixdp425_flash_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #if defined(CONFIG_MTD_NAND_PLATFORM) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)     defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static struct mtd_partition ixdp425_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.name	= "ixp400 NAND FS 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.offset	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.size 	= SZ_8M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.name	= "ixp400 NAND FS 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.offset	= MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.size	= MTDPART_SIZ_FULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) ixdp425_flash_nand_cmd_ctrl(struct nand_chip *this, int cmd, unsigned int ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	int offset = (int)nand_get_controller_data(this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (ctrl & NAND_CTRL_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		if (ctrl & NAND_NCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			gpio_set_value(IXDP425_NAND_NCE_PIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			gpio_set_value(IXDP425_NAND_NCE_PIN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		nand_set_controller_data(this, (void *)offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (cmd != NAND_CMD_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		writeb(cmd, this->legacy.IO_ADDR_W + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct platform_nand_data ixdp425_flash_nand_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.nr_chips		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.chip_delay		= 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.partitions	 	= ixdp425_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.nr_partitions	 	= ARRAY_SIZE(ixdp425_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.ctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.cmd_ctrl 		= ixdp425_flash_nand_cmd_ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct resource ixdp425_flash_nand_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.flags		= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct platform_device ixdp425_flash_nand = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.name		= "gen_nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.id		= -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.dev		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.platform_data = &ixdp425_flash_nand_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.num_resources	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.resource	= &ixdp425_flash_nand_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif	/* CONFIG_MTD_NAND_PLATFORM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct gpiod_lookup_table ixdp425_i2c_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.dev_id		= "i2c-gpio.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.table		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SDA_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SCL_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 				NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct platform_device ixdp425_i2c_gpio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.name		= "i2c-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.id		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.dev	 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.platform_data	= NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct resource ixdp425_uart_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		.start		= IXP4XX_UART1_BASE_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.flags		= IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.start		= IXP4XX_UART2_BASE_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		.flags		= IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct plat_serial8250_port ixdp425_uart_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.mapbase	= IXP4XX_UART1_BASE_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		.irq		= IRQ_IXP4XX_UART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.iotype		= UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		.regshift	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.uartclk	= IXP4XX_UART_XTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.mapbase	= IXP4XX_UART2_BASE_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.irq		= IRQ_IXP4XX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.iotype		= UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		.regshift	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.uartclk	= IXP4XX_UART_XTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct platform_device ixdp425_uart = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.name			= "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.id			= PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.dev.platform_data	= ixdp425_uart_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.num_resources		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.resource		= ixdp425_uart_resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Built-in 10/100 Ethernet MAC interfaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct resource ixp425_npeb_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		.start		= IXP4XX_EthB_BASE_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		.end		= IXP4XX_EthB_BASE_PHYS + 0x0fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		.flags		= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct resource ixp425_npec_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		.start		= IXP4XX_EthC_BASE_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.end		= IXP4XX_EthC_BASE_PHYS + 0x0fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.flags		= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static struct eth_plat_info ixdp425_plat_eth[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.phy		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.rxq		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.txreadyq	= 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		.phy		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		.rxq		= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.txreadyq	= 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct platform_device ixdp425_eth[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		.name			= "ixp4xx_eth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.id			= IXP4XX_ETH_NPEB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.dev.platform_data	= ixdp425_plat_eth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.num_resources		= ARRAY_SIZE(ixp425_npeb_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.resource		= ixp425_npeb_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		.name			= "ixp4xx_eth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.id			= IXP4XX_ETH_NPEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.dev.platform_data	= ixdp425_plat_eth + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		.num_resources		= ARRAY_SIZE(ixp425_npec_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		.resource		= ixp425_npec_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static struct platform_device *ixdp425_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	&ixdp425_i2c_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	&ixdp425_flash,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #if defined(CONFIG_MTD_NAND_PLATFORM) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)     defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	&ixdp425_flash_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	&ixdp425_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	&ixdp425_eth[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	&ixdp425_eth[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void __init ixdp425_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	ixp4xx_sys_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ixdp425_flash_resource.end =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #if defined(CONFIG_MTD_NAND_PLATFORM) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)     defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	ixdp425_flash_nand_resource.end   = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	gpio_request(IXDP425_NAND_NCE_PIN, "NAND NCE pin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	gpio_direction_output(IXDP425_NAND_NCE_PIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* Configure expansion bus for NAND Flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			  IXP4XX_EXP_BUS_STROBE_T(1) |	/* extend by 1 clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			  IXP4XX_EXP_BUS_CYCLES(0) |	/* Intel cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			  IXP4XX_EXP_BUS_SIZE(0) |	/* 512bytes addr space*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			  IXP4XX_EXP_BUS_WR_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			  IXP4XX_EXP_BUS_BYTE_EN;	/* 8 bit data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (cpu_is_ixp43x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		ixdp425_uart.num_resources = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		ixdp425_uart_data[1].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	gpiod_add_lookup_table(&ixdp425_i2c_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #ifdef CONFIG_ARCH_IXDP425
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	/* Maintainer: MontaVista Software, Inc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.map_io		= ixp4xx_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.init_early	= ixp4xx_init_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	.init_irq	= ixp4xx_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.init_time	= ixp4xx_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.atag_offset	= 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.init_machine	= ixdp425_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #if defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.dma_zone_size	= SZ_64M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.restart	= ixp4xx_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #ifdef CONFIG_MACH_IXDP465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	/* Maintainer: MontaVista Software, Inc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.map_io		= ixp4xx_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.init_early	= ixp4xx_init_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.init_irq	= ixp4xx_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.init_time	= ixp4xx_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.atag_offset	= 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.init_machine	= ixdp425_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #if defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.dma_zone_size	= SZ_64M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #ifdef CONFIG_ARCH_PRPMC1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	/* Maintainer: MontaVista Software, Inc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.map_io		= ixp4xx_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.init_early	= ixp4xx_init_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.init_irq	= ixp4xx_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.init_time	= ixp4xx_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.atag_offset	= 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.init_machine	= ixdp425_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #if defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.dma_zone_size	= SZ_64M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #ifdef CONFIG_MACH_KIXRP435
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	/* Maintainer: MontaVista Software, Inc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.map_io		= ixp4xx_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.init_early	= ixp4xx_init_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.init_irq	= ixp4xx_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.init_time	= ixp4xx_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.atag_offset	= 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	.init_machine	= ixdp425_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #if defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.dma_zone_size	= SZ_64M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #endif