Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/arm/mach-ixp4xx/include/mach/irqs.h 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * IRQ definitions for IXP4XX based systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2002 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 2003 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _ARCH_IXP4XX_IRQS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _ARCH_IXP4XX_IRQS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IRQ_IXP4XX_BASE		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IRQ_IXP4XX_NPEA		(IRQ_IXP4XX_BASE + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IRQ_IXP4XX_NPEB		(IRQ_IXP4XX_BASE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IRQ_IXP4XX_NPEC		(IRQ_IXP4XX_BASE + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IRQ_IXP4XX_QM1		(IRQ_IXP4XX_BASE + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IRQ_IXP4XX_QM2		(IRQ_IXP4XX_BASE + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IRQ_IXP4XX_TIMER1	(IRQ_IXP4XX_BASE + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IRQ_IXP4XX_GPIO0	(IRQ_IXP4XX_BASE + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IRQ_IXP4XX_GPIO1	(IRQ_IXP4XX_BASE + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IRQ_IXP4XX_PCI_INT	(IRQ_IXP4XX_BASE + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IRQ_IXP4XX_PCI_DMA1	(IRQ_IXP4XX_BASE + 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IRQ_IXP4XX_PCI_DMA2	(IRQ_IXP4XX_BASE + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IRQ_IXP4XX_TIMER2	(IRQ_IXP4XX_BASE + 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IRQ_IXP4XX_USB		(IRQ_IXP4XX_BASE + 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IRQ_IXP4XX_UART2	(IRQ_IXP4XX_BASE + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IRQ_IXP4XX_TIMESTAMP	(IRQ_IXP4XX_BASE + 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IRQ_IXP4XX_UART1	(IRQ_IXP4XX_BASE + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IRQ_IXP4XX_WDOG		(IRQ_IXP4XX_BASE + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IRQ_IXP4XX_AHB_PMU	(IRQ_IXP4XX_BASE + 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IRQ_IXP4XX_XSCALE_PMU	(IRQ_IXP4XX_BASE + 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IRQ_IXP4XX_GPIO2	(IRQ_IXP4XX_BASE + 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IRQ_IXP4XX_GPIO3	(IRQ_IXP4XX_BASE + 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IRQ_IXP4XX_GPIO4	(IRQ_IXP4XX_BASE + 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IRQ_IXP4XX_GPIO5	(IRQ_IXP4XX_BASE + 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IRQ_IXP4XX_GPIO6	(IRQ_IXP4XX_BASE + 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IRQ_IXP4XX_GPIO7	(IRQ_IXP4XX_BASE + 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IRQ_IXP4XX_GPIO8	(IRQ_IXP4XX_BASE + 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IRQ_IXP4XX_GPIO9	(IRQ_IXP4XX_BASE + 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IRQ_IXP4XX_GPIO10	(IRQ_IXP4XX_BASE + 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IRQ_IXP4XX_GPIO11	(IRQ_IXP4XX_BASE + 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IRQ_IXP4XX_GPIO12	(IRQ_IXP4XX_BASE + 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IRQ_IXP4XX_SW_INT1	(IRQ_IXP4XX_BASE + 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IRQ_IXP4XX_SW_INT2	(IRQ_IXP4XX_BASE + 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IRQ_IXP4XX_USB_HOST	(IRQ_IXP4XX_BASE + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IRQ_IXP4XX_I2C		(IRQ_IXP4XX_BASE + 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IRQ_IXP4XX_SSP		(IRQ_IXP4XX_BASE + 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IRQ_IXP4XX_TSYNC	(IRQ_IXP4XX_BASE + 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IRQ_IXP4XX_EAU_DONE	(IRQ_IXP4XX_BASE + 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IRQ_IXP4XX_SHA_DONE	(IRQ_IXP4XX_BASE + 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IRQ_IXP4XX_SWCP_PE	(IRQ_IXP4XX_BASE + 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IRQ_IXP4XX_QM_PE	(IRQ_IXP4XX_BASE + 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IRQ_IXP4XX_MCU_ECC	(IRQ_IXP4XX_BASE + 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IRQ_IXP4XX_EXP_PE	(IRQ_IXP4XX_BASE + 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define _IXP4XX_GPIO_IRQ(n)	(IRQ_IXP4XX_GPIO ## n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IXP4XX_GPIO_IRQ(n)	_IXP4XX_GPIO_IRQ(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define	XSCALE_PMU_IRQ		(IRQ_IXP4XX_XSCALE_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif