Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/arm/mach-ixp4xx/gtwx5715-pci.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Gemtek GTWX5715 (Linksys WRV54G) board setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2004 George T. Joseph
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Derived from Coyote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SLOT0_DEVID	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SLOT1_DEVID	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define INTA		10 /* slot 1 has INTA and INTB crossed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define INTB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * Slot 0 isn't actually populated with a card connector but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * we initialize it anyway in case a future version has the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * slot populated or someone with good soldering skills has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * some free time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __init gtwx5715_pci_preinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	ixp4xx_pci_preinit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int __init gtwx5715_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	int rc = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	if ((slot == SLOT0_DEVID && pin == 1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	    (slot == SLOT1_DEVID && pin == 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		rc = IXP4XX_GPIO_IRQ(INTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	else if ((slot == SLOT0_DEVID && pin == 2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		 (slot == SLOT1_DEVID && pin == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		rc = IXP4XX_GPIO_IRQ(INTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	       __func__, slot, pin, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct hw_pci gtwx5715_pci __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	.nr_controllers = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	.ops		= &ixp4xx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	.preinit =        gtwx5715_pci_preinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	.setup =          ixp4xx_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	.map_irq =        gtwx5715_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int __init gtwx5715_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	if (machine_is_gtwx5715())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		pci_common_init(&gtwx5715_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) subsys_initcall(gtwx5715_pci_init);