^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-ixp4xx/common-pci.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * IXP4XX PCI routines for all platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Maintainer: Deepak Saxena <dsaxena@plexity.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2002 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2003-2004 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * IXP4xx PCI read function is dependent on whether we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * running A0 or B0 (AppleGate) silicon.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Base address for PCI register region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long ixp4xx_pci_reg_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * PCI cfg an I/O routines are done by programming a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * command/byte enable register, and then read/writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * the data from a data register. We need to ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * these transactions are atomic or we will end up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * with corrupt data on the bus or in a driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Read from PCI config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void crp_read(u32 ad_cbe, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *PCI_CRP_AD_CBE = ad_cbe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *data = *PCI_CRP_RDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Write to PCI config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void crp_write(u32 ad_cbe, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *PCI_CRP_WDATA = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline int check_master_abort(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* check Master Abort bit after access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long isr = *PCI_ISR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (isr & PCI_ISR_PFE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* make sure the Master Abort bit is reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *PCI_ISR = PCI_ISR_PFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pr_debug("%s failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *PCI_NP_AD = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * PCI workaround - only works if NP PCI space reads have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * no side effects!!! Read 8 times. last one will be good.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *PCI_NP_CBE = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *data = *PCI_NP_RDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *data = *PCI_NP_RDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if(check_master_abort())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) retval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *PCI_NP_AD = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* set up and execute the read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *PCI_NP_CBE = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* the result of the read is now in NP_RDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *data = *PCI_NP_RDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if(check_master_abort())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) retval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *PCI_NP_AD = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* set up the write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *PCI_NP_CBE = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* execute the write by writing to NP_WDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *PCI_NP_WDATA = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if(check_master_abort())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) retval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!bus_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* type 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) (where & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* type 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * 0 and 3 are not valid indexes...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static u32 bytemask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*0*/ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*1*/ 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*2*/ 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*3*/ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*4*/ 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static u32 local_byte_lane_enable_bits(u32 n, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (size == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int local_read_config(int where, int size, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 n, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pr_debug("local_read_config from %d size %d\n", where, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) n = where % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) crp_read(where & ~3, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *value = (data >> (8*n)) & bytemask[size];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pr_debug("local_read_config read %#x\n", *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int local_write_config(int where, int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 n, byte_enables, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) n = where % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) byte_enables = local_byte_lane_enable_bits(n, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (byte_enables == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) data = value << (8*n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) crp_write((where & ~3) | byte_enables, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static u32 byte_lane_enable_bits(u32 n, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return (0xf & ~BIT(n)) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (size == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 n, byte_enables, addr, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u8 bus_num = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *value = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) n = where % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) byte_enables = byte_lane_enable_bits(n, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (byte_enables == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) addr = ixp4xx_config_addr(bus_num, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *value = (data >> (8*n)) & bytemask[size];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pr_debug("read_config_byte read %#x\n", *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 n, byte_enables, addr, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 bus_num = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) n = where % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) byte_enables = byte_lane_enable_bits(n, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (byte_enables == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) addr = ixp4xx_config_addr(bus_num, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) data = value << (8*n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct pci_ops ixp4xx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .read = ixp4xx_pci_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .write = ixp4xx_pci_write_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * PCI abort handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 isr, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) isr = *PCI_ISR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) local_read_config(PCI_STATUS, 2, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "status = %#x\n", addr, isr, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* make sure the Master Abort bit is reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) *PCI_ISR = PCI_ISR_PFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) status |= PCI_STATUS_REC_MASTER_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) local_write_config(PCI_STATUS, 2, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * If it was an imprecise abort, then we need to correct the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * return address to be _after_ the instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (fsr & (1 << 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) regs->ARM_pc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) void __init ixp4xx_pci_preinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned long cpuid = read_cpuid_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #ifdef CONFIG_IXP4XX_INDIRECT_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Determine which PCI read method to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Rev 0 IXP425 requires workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) printk("PCI: IXP42x A0 silicon detected - "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "PCI Non-Prefetch Workaround Enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ixp4xx_pci_read = ixp4xx_pci_read_errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ixp4xx_pci_read = ixp4xx_pci_read_no_errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* hook in our fault handler for PCI errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) hook_fault_code(16+6, abort_handler, SIGBUS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "imprecise external abort");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * We use identity AHB->PCI address translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * in the 0x48000000 to 0x4bffffff address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) *PCI_PCIMEMBASE = 0x48494A4B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * We also use identity PCI->AHB address translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * in 4 16MB BARs that begin at the physical memory start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ((PHYS_OFFSET & 0xFF000000) >> 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ((PHYS_OFFSET & 0xFF000000) >> 16) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ((PHYS_OFFSET & 0xFF000000) >> 24) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 0x00010203;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (*PCI_CSR & PCI_CSR_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) printk("PCI: IXP4xx is host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pr_debug("setup BARs in controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * We configure the PCI inbound memory windows to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * 1:1 mapped to SDRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) local_write_config(PCI_BASE_ADDRESS_3, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PHYS_OFFSET + SZ_32M + SZ_16M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Enable CSR window at 64 MiB to allow PCI masters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * to continue prefetching past 64 MiB boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Enable the IO window to be way up high, at 0xfffffc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) local_write_config(0x40, 4, 0x000080FF); /* No TRDY time limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) printk("PCI: IXP4xx is target - No bus scan performed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) printk("PCI: IXP4xx Using %s access for memory space\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #ifndef CONFIG_IXP4XX_INDIRECT_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) "direct"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "indirect"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pr_debug("clear error bits in ISR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) *PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Set Initialize Complete in PCI Control Register: allow IXP4XX to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * respond to PCI configuration cycles. Specify that the AHB bus is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * operating in big endian mode. Set up byte lane swapping between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * little-endian PCI and the big-endian AHB bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #ifdef __ARMEB__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pr_debug("DONE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int ixp4xx_setup(int nr, struct pci_sys_data *sys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (nr >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) res = kcalloc(2, sizeof(*res), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (res == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * If we're out of memory this early, something is wrong,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * so we might as well catch it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) panic("PCI: unable to allocate resources?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) res[0].name = "PCI I/O Space";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) res[0].start = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) res[0].end = 0x0000ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) res[0].flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) res[1].name = "PCI Memory Space";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) res[1].start = PCIBIOS_MIN_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) res[1].end = PCIBIOS_MAX_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) res[1].flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) request_resource(&ioport_resource, &res[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) request_resource(&iomem_resource, &res[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) EXPORT_SYMBOL(ixp4xx_pci_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) EXPORT_SYMBOL(ixp4xx_pci_write);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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