Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/arm/mach-ixp4xx/avila-pci.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Gateworks Avila board-level PCI initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Author: Michael-Luke Jones <mlj28@cam.ac.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Based on ixdp-pci.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * Copyright (C) 2002 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * Copyright (C) 2003-2004 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AVILA_MAX_DEV	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LOFT_MAX_DEV	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IRQ_LINES	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* PCI controller GPIO to IRQ pin mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define INTA		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define INTB		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define INTC		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define INTD		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __init avila_pci_preinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	ixp4xx_pci_preinit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int __init avila_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	static int pci_irq_table[IRQ_LINES] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		IXP4XX_GPIO_IRQ(INTA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		IXP4XX_GPIO_IRQ(INTB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		IXP4XX_GPIO_IRQ(INTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		IXP4XX_GPIO_IRQ(INTD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	if (slot >= 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	    slot <= (machine_is_loft() ? LOFT_MAX_DEV : AVILA_MAX_DEV) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	    pin >= 1 && pin <= IRQ_LINES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		return pci_irq_table[(slot + pin - 2) % 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct hw_pci avila_pci __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	.nr_controllers = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	.ops		= &ixp4xx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	.preinit	= avila_pci_preinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	.setup		= ixp4xx_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	.map_irq	= avila_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int __init avila_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	if (machine_is_avila() || machine_is_loft())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 		pci_common_init(&avila_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) subsys_initcall(avila_pci_init);