Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Author:	Rory Bolt <rorybolt@pacbell.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright:	(C) 2002 Rory Bolt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __IOP32X_IRQS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __IOP32X_IRQS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* Interrupts in Linux start at 1, hardware starts at 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IOP_IRQ(x) ((x) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * IOP80321 chipset interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IRQ_IOP32X_DMA0_EOT	IOP_IRQ(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IRQ_IOP32X_DMA0_EOC	IOP_IRQ(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IRQ_IOP32X_DMA1_EOT	IOP_IRQ(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IRQ_IOP32X_DMA1_EOC	IOP_IRQ(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IRQ_IOP32X_AA_EOT	IOP_IRQ(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IRQ_IOP32X_AA_EOC	IOP_IRQ(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IRQ_IOP32X_CORE_PMON	IOP_IRQ(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IRQ_IOP32X_TIMER0	IOP_IRQ(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IRQ_IOP32X_TIMER1	IOP_IRQ(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IRQ_IOP32X_I2C_0	IOP_IRQ(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IRQ_IOP32X_I2C_1	IOP_IRQ(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IRQ_IOP32X_MESSAGING	IOP_IRQ(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IRQ_IOP32X_ATU_BIST	IOP_IRQ(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IRQ_IOP32X_PERFMON	IOP_IRQ(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IRQ_IOP32X_CORE_PMU	IOP_IRQ(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IRQ_IOP32X_BIU_ERR	IOP_IRQ(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IRQ_IOP32X_ATU_ERR	IOP_IRQ(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IRQ_IOP32X_MCU_ERR	IOP_IRQ(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IRQ_IOP32X_DMA0_ERR	IOP_IRQ(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IRQ_IOP32X_DMA1_ERR	IOP_IRQ(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IRQ_IOP32X_AA_ERR	IOP_IRQ(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IRQ_IOP32X_MSG_ERR	IOP_IRQ(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IRQ_IOP32X_SSP		IOP_IRQ(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IRQ_IOP32X_XINT0	IOP_IRQ(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IRQ_IOP32X_XINT1	IOP_IRQ(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IRQ_IOP32X_XINT2	IOP_IRQ(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IRQ_IOP32X_XINT3	IOP_IRQ(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IRQ_IOP32X_HPI		IOP_IRQ(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #endif