Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/arm/mach-iop32x/irq.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Generic IOP32X IRQ handling functionality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Author: Rory Bolt <rorybolt@pacbell.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 2002 Rory Bolt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static u32 iop32x_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static void intctl_write(u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void intstr_write(u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) iop32x_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	iop32x_mask &= ~(1 << (d->irq - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	intctl_write(iop32x_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) iop32x_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	iop32x_mask |= 1 << (d->irq - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	intctl_write(iop32x_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct irq_chip ext_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	.name		= "IOP32x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	.irq_ack	= iop32x_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	.irq_mask	= iop32x_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	.irq_unmask	= iop32x_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __init iop32x_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	iop_init_cp6_handler();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	intctl_write(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	intstr_write(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	if (machine_is_glantank() ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	    machine_is_iq80321() ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	    machine_is_iq31244() ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	    machine_is_n2100() ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	    machine_is_em7210())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		*IOP3XX_PCIIRSR = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	for (i = 1; i < NR_IRQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }