Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Intel IOP32X and IOP33X register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Rory Bolt <rorybolt@pacbell.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2002 Rory Bolt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2004 Intel Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef __IOP3XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define __IOP3XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Peripherals that are shared between the iop32x and iop33x but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * located at different addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IOP3XX_TIMER_REG(reg)	(IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "iop3xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* ATU Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * set up a 1:1 bus to physical ram relationship
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * w/ physical ram on top of pci in the memory map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IOP32X_MAX_RAM_SIZE            0x40000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IOP3XX_MAX_RAM_SIZE            IOP32X_MAX_RAM_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IOP3XX_PCI_LOWER_MEM_BA        0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * IOP3XX GPIO handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IOP3XX_GPIO_LINE(x)	(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) extern int init_atu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) extern int iop3xx_get_init_atu(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * IOP3XX processor registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IOP3XX_PERIPHERAL_PHYS_BASE	0xffffe000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IOP3XX_PERIPHERAL_VIRT_BASE	0xfedfe000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IOP3XX_PERIPHERAL_SIZE		0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 					IOP3XX_PERIPHERAL_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 					IOP3XX_PERIPHERAL_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 					(IOP3XX_PERIPHERAL_PHYS_BASE\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 					- IOP3XX_PERIPHERAL_VIRT_BASE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define IOP3XX_REG_ADDR(reg)		(IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* Address Translation Unit  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define IOP3XX_ATUVID		(volatile u16 *)IOP3XX_REG_ADDR(0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define IOP3XX_ATUDID		(volatile u16 *)IOP3XX_REG_ADDR(0x0102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define IOP3XX_ATUCMD		(volatile u16 *)IOP3XX_REG_ADDR(0x0104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IOP3XX_ATUSR		(volatile u16 *)IOP3XX_REG_ADDR(0x0106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IOP3XX_ATURID		(volatile u8  *)IOP3XX_REG_ADDR(0x0108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define IOP3XX_ATUCCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define IOP3XX_ATUCLSR		(volatile u8  *)IOP3XX_REG_ADDR(0x010c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IOP3XX_ATULT		(volatile u8  *)IOP3XX_REG_ADDR(0x010d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IOP3XX_ATUHTR		(volatile u8  *)IOP3XX_REG_ADDR(0x010e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define IOP3XX_ATUBIST		(volatile u8  *)IOP3XX_REG_ADDR(0x010f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define IOP3XX_IABAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IOP3XX_IAUBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define IOP3XX_IABAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define IOP3XX_IAUBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x011c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define IOP3XX_IABAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IOP3XX_IAUBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define IOP3XX_ASVIR		(volatile u16 *)IOP3XX_REG_ADDR(0x012c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define IOP3XX_ASIR		(volatile u16 *)IOP3XX_REG_ADDR(0x012e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define IOP3XX_ERBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define IOP3XX_ATUILR		(volatile u8  *)IOP3XX_REG_ADDR(0x013c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define IOP3XX_ATUIPR		(volatile u8  *)IOP3XX_REG_ADDR(0x013d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define IOP3XX_ATUMGNT		(volatile u8  *)IOP3XX_REG_ADDR(0x013e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define IOP3XX_ATUMLAT		(volatile u8  *)IOP3XX_REG_ADDR(0x013f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define IOP3XX_IALR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define IOP3XX_IATVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define IOP3XX_ERLR		(volatile u32 *)IOP3XX_REG_ADDR(0x0148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define IOP3XX_ERTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x014c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define IOP3XX_IALR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IOP3XX_IALR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define IOP3XX_IATVR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define IOP3XX_OIOWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x015c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define IOP3XX_OMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define IOP3XX_OUMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define IOP3XX_OMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define IOP3XX_OUMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x016c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define IOP3XX_OUDWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x0178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define IOP3XX_ATUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define IOP3XX_PCSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define IOP3XX_ATUISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define IOP3XX_ATUIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x018c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define IOP3XX_IABAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define IOP3XX_IAUBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define IOP3XX_IALR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define IOP3XX_IATVR3		(volatile u32 *)IOP3XX_REG_ADDR(0x019c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IOP3XX_OCCAR		(volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IOP3XX_OCCDR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IOP3XX_PDSCR		(volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IOP3XX_PMCAPID		(volatile u8  *)IOP3XX_REG_ADDR(0x01c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IOP3XX_PMNEXT		(volatile u8  *)IOP3XX_REG_ADDR(0x01c1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IOP3XX_APMCR		(volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IOP3XX_APMCSR		(volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IOP3XX_PCIXCAPID	(volatile u8  *)IOP3XX_REG_ADDR(0x01e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IOP3XX_PCIXNEXT		(volatile u8  *)IOP3XX_REG_ADDR(0x01e1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IOP3XX_PCIXCMD		(volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IOP3XX_PCIXSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IOP3XX_PCIIRSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IOP3XX_PCSR_IN_Q_BUSY	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IOP3XX_ATUCR_OUT_EN	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IOP3XX_INIT_ATU_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IOP3XX_INIT_ATU_DISABLE -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IOP3XX_INIT_ATU_ENABLE	 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Messaging Unit  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IOP3XX_IMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IOP3XX_IMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IOP3XX_OMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IOP3XX_OMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x031c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IOP3XX_IDR		(volatile u32 *)IOP3XX_REG_ADDR(0x0320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IOP3XX_IISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IOP3XX_IIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IOP3XX_ODR		(volatile u32 *)IOP3XX_REG_ADDR(0x032c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IOP3XX_OISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IOP3XX_OIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IOP3XX_MUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IOP3XX_QBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IOP3XX_IFHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IOP3XX_IFTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IOP3XX_IPHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IOP3XX_IPTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x036c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IOP3XX_OFHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IOP3XX_OFTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IOP3XX_OPHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IOP3XX_OPTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x037c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IOP3XX_IAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* DMA Controller  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 					(0x400 + (chan << 6)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IOP3XX_DMA_UPPER_PA(chan)  (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Peripheral bus interface  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IOP3XX_PBCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IOP3XX_PBISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IOP3XX_PBBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IOP3XX_PBLR0		(volatile u32 *)IOP3XX_REG_ADDR(0x068c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IOP3XX_PBBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IOP3XX_PBLR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IOP3XX_PBBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IOP3XX_PBLR2		(volatile u32 *)IOP3XX_REG_ADDR(0x069c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IOP3XX_PBBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IOP3XX_PBLR3		(volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IOP3XX_PBBAR4		(volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IOP3XX_PBLR4		(volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IOP3XX_PBBAR5		(volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IOP3XX_PBLR5		(volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IOP3XX_PMBR0		(volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IOP3XX_PMBR1		(volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IOP3XX_PMBR2		(volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Peripheral performance monitoring unit  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IOP3XX_GTMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IOP3XX_ESR		(volatile u32 *)IOP3XX_REG_ADDR(0x0704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IOP3XX_EMISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IOP3XX_GTSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* PERCR0 DOESN'T EXIST - index from 1! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IOP3XX_PERCR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Timers  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IOP3XX_TU_TMR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IOP3XX_TU_TMR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IOP3XX_TU_TCR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IOP3XX_TU_TCR1		(volatile u32 *)IOP3XX_TIMER_REG(0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IOP3XX_TU_TRR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IOP3XX_TU_TRR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IOP3XX_TU_TISR		(volatile u32 *)IOP3XX_TIMER_REG(0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IOP3XX_TU_WDTCR		(volatile u32 *)IOP3XX_TIMER_REG(0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IOP_TMR_EN	    0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IOP_TMR_RELOAD	    0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IOP_TMR_PRIVILEGED 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IOP_TMR_RATIO_1_1  0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Watchdog timer definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IOP_WDTCR_EN_ARM        0x1e1e1e1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IOP_WDTCR_EN            0xe1e1e1e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* iop3xx does not support stopping the watchdog, so we just re-arm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IOP_WDTCR_DIS_ARM	(IOP_WDTCR_EN_ARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IOP_WDTCR_DIS		(IOP_WDTCR_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Application accelerator unit  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* I2C bus interface unit  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IOP3XX_ICR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IOP3XX_ISR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IOP3XX_ISAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IOP3XX_IDBR0		(volatile u32 *)IOP3XX_REG_ADDR(0x168c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IOP3XX_IBMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IOP3XX_ICR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IOP3XX_ISR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IOP3XX_ISAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IOP3XX_IDBR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IOP3XX_IBMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  * IOP3XX I/O and Mem space regions for PCI autoconfiguration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IOP3XX_PCI_LOWER_MEM_PA	0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IOP3XX_PCI_MEM_WINDOW_SIZE	0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IOP3XX_PCI_LOWER_IO_PA		0x90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IOP3XX_PCI_LOWER_IO_BA		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) void iop3xx_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) void iop_init_cp6_handler(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) void iop_init_time(unsigned long tickrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void iop3xx_restart(enum reboot_mode, const char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static inline u32 read_tmr0(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static inline void write_tmr0(u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static inline void write_tmr1(u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static inline u32 read_tcr0(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline void write_tcr0(u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static inline u32 read_tcr1(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static inline void write_tcr1(u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static inline void write_trr0(u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static inline void write_trr1(u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static inline void write_tisr(u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static inline u32 read_wdtcr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static inline void write_wdtcr(u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) extern unsigned long get_iop_tick_rate(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* only iop13xx has these registers, we define these to present a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)  * common register interface for the iop_wdt driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define IOP_RCSR_WDT	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static inline u32 read_rcsr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static inline void write_wdtsr(u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	do { } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) extern struct platform_device iop3xx_dma_0_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) extern struct platform_device iop3xx_dma_1_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) extern struct platform_device iop3xx_aau_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) extern struct platform_device iop3xx_i2c0_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) extern struct platform_device iop3xx_i2c1_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) extern struct gpiod_lookup_table iop3xx_i2c0_gpio_lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) extern struct gpiod_lookup_table iop3xx_i2c1_gpio_lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #endif