^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-iop32x/glantank.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Board support code for the GLAN Tank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2006, 2007 Martin Michlmayr <tbm@cyrius.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/f75375s.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "gpio-iop32x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * GLAN Tank timer tick configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void __init glantank_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* 33.333 MHz crystal. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) iop_init_time(200000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * GLAN Tank I/O.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct map_desc glantank_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { /* on-board devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .virtual = GLANTANK_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .pfn = __phys_to_pfn(GLANTANK_UART),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .length = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __init glantank_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) iop3xx_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) iotable_init(glantank_io_desc, ARRAY_SIZE(glantank_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * GLAN Tank PCI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define INTA IRQ_IOP32X_XINT0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define INTB IRQ_IOP32X_XINT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define INTC IRQ_IOP32X_XINT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define INTD IRQ_IOP32X_XINT3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) glantank_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int pci_irq_table[][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * PCI IDSEL/INTPIN->INTLINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * A B C D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {INTD, INTD, INTD, INTD}, /* UART (8250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {INTA, INTA, INTA, INTA}, /* Ethernet (E1000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {INTB, INTB, INTB, INTB}, /* IDE (AEC6280R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {INTC, INTC, INTC, INTC}, /* USB (NEC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) BUG_ON(pin < 1 || pin > 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return pci_irq_table[slot % 4][pin - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static struct hw_pci glantank_pci __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .nr_controllers = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .ops = &iop3xx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .setup = iop3xx_pci_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .preinit = iop3xx_pci_preinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .map_irq = glantank_pci_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int __init glantank_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (machine_is_glantank())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pci_common_init(&glantank_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) subsys_initcall(glantank_pci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * GLAN Tank machine initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct physmap_flash_data glantank_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct resource glantank_flash_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .start = 0xf0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .end = 0xf007ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct platform_device glantank_flash_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .platform_data = &glantank_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .resource = &glantank_flash_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static struct plat_serial8250_port glantank_serial_port[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .mapbase = GLANTANK_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .membase = (char *)GLANTANK_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .irq = IRQ_IOP32X_XINT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .flags = UPF_SKIP_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .regshift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .uartclk = 1843200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct resource glantank_uart_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .start = GLANTANK_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .end = GLANTANK_UART + 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct platform_device glantank_serial_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .id = PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .platform_data = glantank_serial_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .resource = &glantank_uart_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct f75375s_platform_data glantank_f75375s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .pwm = { 255, 255 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .pwm_enable = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct i2c_board_info __initdata glantank_i2c_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) I2C_BOARD_INFO("rs5c372a", 0x32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) I2C_BOARD_INFO("f75375", 0x2e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .platform_data = &glantank_f75375s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void glantank_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __raw_writeb(0x01, IOMEM(0xfe8d0004));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void __init glantank_init_machine(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) register_iop32x_gpio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) platform_device_register(&iop3xx_i2c0_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) platform_device_register(&iop3xx_i2c1_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) platform_device_register(&glantank_flash_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) platform_device_register(&glantank_serial_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) platform_device_register(&iop3xx_dma_0_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) platform_device_register(&iop3xx_dma_1_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) i2c_register_board_info(0, glantank_i2c_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ARRAY_SIZE(glantank_i2c_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pm_power_off = glantank_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MACHINE_START(GLANTANK, "GLAN Tank")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .map_io = glantank_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .init_irq = iop32x_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .init_time = glantank_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .init_machine = glantank_init_machine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .restart = iop3xx_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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