^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * platform device definitions for the iop3xx dma/xor engines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright © 2006, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_data/dma-iop32x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "iop3xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IRQ_AA_EOT IRQ_IOP32X_AA_EOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IRQ_AA_EOC IRQ_IOP32X_AA_EOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IRQ_AA_ERR IRQ_IOP32X_AA_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* AAU and DMA Channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct resource iop3xx_dma_0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .start = IOP3XX_DMA_PHYS_BASE(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .end = IOP3XX_DMA_UPPER_PA(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .start = IRQ_DMA0_EOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .end = IRQ_DMA0_EOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .flags = IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .start = IRQ_DMA0_EOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .end = IRQ_DMA0_EOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .flags = IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .start = IRQ_DMA0_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .end = IRQ_DMA0_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .flags = IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct resource iop3xx_dma_1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .start = IOP3XX_DMA_PHYS_BASE(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .end = IOP3XX_DMA_UPPER_PA(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .start = IRQ_DMA1_EOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .end = IRQ_DMA1_EOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .flags = IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .start = IRQ_DMA1_EOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .end = IRQ_DMA1_EOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .flags = IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .start = IRQ_DMA1_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .end = IRQ_DMA1_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .flags = IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct resource iop3xx_aau_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .start = IOP3XX_AAU_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .end = IOP3XX_AAU_UPPER_PA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .start = IRQ_AA_EOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .end = IRQ_AA_EOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .flags = IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .start = IRQ_AA_EOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .end = IRQ_AA_EOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .flags = IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .start = IRQ_AA_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .end = IRQ_AA_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .flags = IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static u64 iop3xx_adma_dmamask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct iop_adma_platform_data iop3xx_dma_0_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .hw_id = DMA0_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .pool_size = PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct iop_adma_platform_data iop3xx_dma_1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .hw_id = DMA1_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .pool_size = PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct iop_adma_platform_data iop3xx_aau_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .hw_id = AAU_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .pool_size = 3 * PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct platform_device iop3xx_dma_0_channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "iop-adma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .num_resources = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .resource = iop3xx_dma_0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .dma_mask = &iop3xx_adma_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .platform_data = (void *) &iop3xx_dma_0_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct platform_device iop3xx_dma_1_channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .name = "iop-adma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .num_resources = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .resource = iop3xx_dma_1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .dma_mask = &iop3xx_adma_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .platform_data = (void *) &iop3xx_dma_1_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct platform_device iop3xx_aau_channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .name = "iop-adma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .id = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .num_resources = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .resource = iop3xx_aau_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .dma_mask = &iop3xx_adma_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .platform_data = (void *) &iop3xx_aau_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int __init iop3xx_adma_cap_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) arch_initcall(iop3xx_adma_cap_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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