Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  This file contains the hardware definitions of the Integrator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 1998-1999 ARM Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef INTEGRATOR_HARDWARE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define INTEGRATOR_HARDWARE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Where in virtual memory the IO devices (timers, system controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * and so on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define IO_BASE			0xF0000000                 // VA of IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define IO_SIZE			0x0B000000                 // How much?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define IO_START		INTEGRATOR_HDR_BASE        // PA of IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* macro to get at IO space when running virtually */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IO_ADDRESS(x)	(((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IO_ADDRESS(x)	(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define __io_address(n)		((void __iomem *)IO_ADDRESS(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *  Integrator memory map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define INTEGRATOR_BOOT_ROM_LO          0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define INTEGRATOR_BOOT_ROM_HI          0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define INTEGRATOR_BOOT_ROM_BASE        INTEGRATOR_BOOT_ROM_HI	 /*  Normal position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define INTEGRATOR_BOOT_ROM_SIZE        SZ_512K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * New Core Modules have different amounts of SSRAM, the amount of SSRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * fitted can be found in HDR_STAT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * the minimum amount of SSRAM fitted on any core module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * New Core Modules also alias the SSRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define INTEGRATOR_SSRAM_BASE           0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define INTEGRATOR_SSRAM_ALIAS_BASE     0x10800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define INTEGRATOR_SSRAM_SIZE           SZ_256K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define INTEGRATOR_FLASH_BASE           0x24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define INTEGRATOR_FLASH_SIZE           SZ_32M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define INTEGRATOR_MBRD_SSRAM_BASE      0x28000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define INTEGRATOR_MBRD_SSRAM_SIZE      SZ_512K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  *  SDRAM is a SIMM therefore the size is not known.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define INTEGRATOR_SDRAM_BASE           0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define INTEGRATOR_SDRAM_ALIAS_BASE     0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define INTEGRATOR_HDR0_SDRAM_BASE      0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define INTEGRATOR_HDR1_SDRAM_BASE      0x90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define INTEGRATOR_HDR2_SDRAM_BASE      0xA0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define INTEGRATOR_HDR3_SDRAM_BASE      0xB0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *  Logic expansion modules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define INTEGRATOR_LOGIC_MODULES_BASE   0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define INTEGRATOR_LOGIC_MODULE0_BASE   0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define INTEGRATOR_LOGIC_MODULE1_BASE   0xD0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define INTEGRATOR_LOGIC_MODULE2_BASE   0xE0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define INTEGRATOR_LOGIC_MODULE3_BASE   0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * Integrator header card registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define INTEGRATOR_HDR_ID_OFFSET        0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define INTEGRATOR_HDR_PROC_OFFSET      0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define INTEGRATOR_HDR_OSC_OFFSET       0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define INTEGRATOR_HDR_CTRL_OFFSET      0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define INTEGRATOR_HDR_STAT_OFFSET      0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define INTEGRATOR_HDR_LOCK_OFFSET      0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define INTEGRATOR_HDR_SDRAM_OFFSET     0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define INTEGRATOR_HDR_INIT_OFFSET      0x24	 /*  CM9x6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define INTEGRATOR_HDR_IC_OFFSET        0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define INTEGRATOR_HDR_SPDBASE_OFFSET   0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define INTEGRATOR_HDR_SPDTOP_OFFSET    0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define INTEGRATOR_HDR_BASE             0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define INTEGRATOR_HDR_ID               (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define INTEGRATOR_HDR_PROC             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define INTEGRATOR_HDR_OSC              (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define INTEGRATOR_HDR_CTRL             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define INTEGRATOR_HDR_STAT             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define INTEGRATOR_HDR_LOCK             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define INTEGRATOR_HDR_SDRAM            (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define INTEGRATOR_HDR_INIT             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define INTEGRATOR_HDR_IC               (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define INTEGRATOR_HDR_SPDBASE          (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define INTEGRATOR_HDR_SPDTOP           (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define INTEGRATOR_HDR_CTRL_LED         0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define INTEGRATOR_HDR_CTRL_REMAP       0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define INTEGRATOR_HDR_CTRL_RESET       0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define INTEGRATOR_HDR_CTRL_BIG_ENDIAN  0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define INTEGRATOR_HDR_CTRL_FASTBUS     0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define INTEGRATOR_HDR_CTRL_SYNC        0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define INTEGRATOR_HDR_OSC_CORE_10MHz   0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define INTEGRATOR_HDR_OSC_CORE_15MHz   0x107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define INTEGRATOR_HDR_OSC_CORE_20MHz   0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define INTEGRATOR_HDR_OSC_CORE_25MHz   0x111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define INTEGRATOR_HDR_OSC_CORE_30MHz   0x116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define INTEGRATOR_HDR_OSC_CORE_35MHz   0x11B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define INTEGRATOR_HDR_OSC_CORE_40MHz   0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define INTEGRATOR_HDR_OSC_CORE_45MHz   0x125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define INTEGRATOR_HDR_OSC_CORE_50MHz   0x12A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define INTEGRATOR_HDR_OSC_CORE_55MHz   0x12F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define INTEGRATOR_HDR_OSC_CORE_60MHz   0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define INTEGRATOR_HDR_OSC_CORE_65MHz   0x139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define INTEGRATOR_HDR_OSC_CORE_70MHz   0x13E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define INTEGRATOR_HDR_OSC_CORE_75MHz   0x143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define INTEGRATOR_HDR_OSC_CORE_80MHz   0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define INTEGRATOR_HDR_OSC_CORE_85MHz   0x14D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define INTEGRATOR_HDR_OSC_CORE_90MHz   0x152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define INTEGRATOR_HDR_OSC_CORE_95MHz   0x157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define INTEGRATOR_HDR_OSC_CORE_100MHz  0x15C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define INTEGRATOR_HDR_OSC_CORE_105MHz  0x161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define INTEGRATOR_HDR_OSC_CORE_110MHz  0x166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define INTEGRATOR_HDR_OSC_CORE_115MHz  0x16B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define INTEGRATOR_HDR_OSC_CORE_120MHz  0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define INTEGRATOR_HDR_OSC_CORE_125MHz  0x175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define INTEGRATOR_HDR_OSC_CORE_130MHz  0x17A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define INTEGRATOR_HDR_OSC_CORE_135MHz  0x17F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define INTEGRATOR_HDR_OSC_CORE_140MHz  0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define INTEGRATOR_HDR_OSC_CORE_145MHz  0x189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define INTEGRATOR_HDR_OSC_CORE_150MHz  0x18E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define INTEGRATOR_HDR_OSC_CORE_155MHz  0x193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define INTEGRATOR_HDR_OSC_CORE_160MHz  0x198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define INTEGRATOR_HDR_OSC_CORE_MASK    0x7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define INTEGRATOR_HDR_OSC_MEM_10MHz    0x10C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define INTEGRATOR_HDR_OSC_MEM_15MHz    0x116000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define INTEGRATOR_HDR_OSC_MEM_20MHz    0x120000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define INTEGRATOR_HDR_OSC_MEM_25MHz    0x12A000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define INTEGRATOR_HDR_OSC_MEM_30MHz    0x134000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define INTEGRATOR_HDR_OSC_MEM_33MHz    0x13A000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define INTEGRATOR_HDR_OSC_MEM_40MHz    0x148000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define INTEGRATOR_HDR_OSC_MEM_50MHz    0x15C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define INTEGRATOR_HDR_OSC_MEM_60MHz    0x170000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define INTEGRATOR_HDR_OSC_MEM_66MHz    0x17C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define INTEGRATOR_HDR_OSC_MEM_MASK     0x7FF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0  0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0  0x0800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6  0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00  0x1800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define INTEGRATOR_HDR_OSC_BUS_MODE_MASK  0x1800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define INTEGRATOR_HDR_SDRAM_SPD_OK     (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * Integrator system registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  *  System Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define INTEGRATOR_SC_ID_OFFSET         0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define INTEGRATOR_SC_OSC_OFFSET        0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define INTEGRATOR_SC_CTRLS_OFFSET      0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define INTEGRATOR_SC_CTRLC_OFFSET      0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define INTEGRATOR_SC_DEC_OFFSET        0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define INTEGRATOR_SC_ARB_OFFSET        0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define INTEGRATOR_SC_LOCK_OFFSET       0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define INTEGRATOR_SC_BASE              0x11000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define INTEGRATOR_SC_ID                (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define INTEGRATOR_SC_OSC               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define INTEGRATOR_SC_CTRLS             (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define INTEGRATOR_SC_CTRLC             (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define INTEGRATOR_SC_DEC               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define INTEGRATOR_SC_ARB               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define INTEGRATOR_SC_PCIENABLE         (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define INTEGRATOR_SC_LOCK              (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define INTEGRATOR_SC_OSC_SYS_10MHz     0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define INTEGRATOR_SC_OSC_SYS_15MHz     0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define INTEGRATOR_SC_OSC_SYS_20MHz     0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define INTEGRATOR_SC_OSC_SYS_25MHz     0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define INTEGRATOR_SC_OSC_SYS_33MHz     0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define INTEGRATOR_SC_OSC_SYS_MASK      0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define INTEGRATOR_SC_OSC_PCI_25MHz     0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define INTEGRATOR_SC_OSC_PCI_33MHz     0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define INTEGRATOR_SC_OSC_PCI_MASK      0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define INTEGRATOR_SC_CTRL_SOFTRST      (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define INTEGRATOR_SC_CTRL_nFLVPPEN     (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define INTEGRATOR_SC_CTRL_nFLWP        (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define INTEGRATOR_SC_CTRL_URTS0        (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define INTEGRATOR_SC_CTRL_UDTR0        (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define INTEGRATOR_SC_CTRL_URTS1        (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define INTEGRATOR_SC_CTRL_UDTR1        (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  *  External Bus Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define INTEGRATOR_EBI_BASE             0x12000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define INTEGRATOR_EBI_CSR0_OFFSET      0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define INTEGRATOR_EBI_CSR1_OFFSET      0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define INTEGRATOR_EBI_CSR2_OFFSET      0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define INTEGRATOR_EBI_CSR3_OFFSET      0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define INTEGRATOR_EBI_LOCK_OFFSET      0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define INTEGRATOR_EBI_CSR0             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define INTEGRATOR_EBI_CSR1             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define INTEGRATOR_EBI_CSR2             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define INTEGRATOR_EBI_CSR3             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define INTEGRATOR_EBI_LOCK             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define INTEGRATOR_EBI_8_BIT            0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define INTEGRATOR_EBI_16_BIT           0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define INTEGRATOR_EBI_32_BIT           0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define INTEGRATOR_EBI_WRITE_ENABLE     0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define INTEGRATOR_EBI_SYNC             0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define INTEGRATOR_EBI_WS_2             0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define INTEGRATOR_EBI_WS_3             0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define INTEGRATOR_EBI_WS_4             0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define INTEGRATOR_EBI_WS_5             0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define INTEGRATOR_EBI_WS_6             0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define INTEGRATOR_EBI_WS_7             0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define INTEGRATOR_EBI_WS_8             0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define INTEGRATOR_EBI_WS_9             0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define INTEGRATOR_EBI_WS_10            0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define INTEGRATOR_EBI_WS_11            0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define INTEGRATOR_EBI_WS_12            0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define INTEGRATOR_EBI_WS_13            0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define INTEGRATOR_EBI_WS_14            0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define INTEGRATOR_EBI_WS_15            0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define INTEGRATOR_EBI_WS_16            0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define INTEGRATOR_EBI_WS_17            0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define INTEGRATOR_CT_BASE              0x13000000	 /*  Counter/Timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define INTEGRATOR_IC_BASE              0x14000000	 /*  Interrupt Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define INTEGRATOR_RTC_BASE             0x15000000	 /*  Real Time Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define INTEGRATOR_UART0_BASE           0x16000000	 /*  UART 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define INTEGRATOR_UART1_BASE           0x17000000	 /*  UART 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define INTEGRATOR_KBD_BASE             0x18000000	 /*  Keyboard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define INTEGRATOR_MOUSE_BASE           0x19000000	 /*  Mouse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  *  LED's & Switches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define INTEGRATOR_DBG_ALPHA_OFFSET     0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define INTEGRATOR_DBG_LEDS_OFFSET      0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define INTEGRATOR_DBG_SWITCH_OFFSET    0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define INTEGRATOR_DBG_BASE             0x1A000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define INTEGRATOR_DBG_ALPHA            (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define INTEGRATOR_DBG_LEDS             (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define INTEGRATOR_DBG_SWITCH           (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define INTEGRATOR_AP_GPIO_BASE		0x1B000000	/* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define INTEGRATOR_CP_MMC_BASE		0x1C000000	/* MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define INTEGRATOR_CP_AACI_BASE		0x1D000000	/* AACI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define INTEGRATOR_CP_ETH_BASE		0xC8000000	/* Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define INTEGRATOR_CP_GPIO_BASE		0xC9000000	/* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define INTEGRATOR_CP_SIC_BASE		0xCA000000	/* SIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define INTEGRATOR_CP_CTL_BASE		0xCB000000	/* CP system control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* PS2 Keyboard interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define KMI0_BASE                       INTEGRATOR_KBD_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* PS2 Mouse interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define KMI1_BASE                       INTEGRATOR_MOUSE_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  * Integrator Interrupt Controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  * Offsets from interrupt controller base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)  * System Controller interrupt controller base is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)  * 	INTEGRATOR_IC_BASE + (header_number << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)  * Core Module interrupt controller base is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)  * 	INTEGRATOR_HDR_IC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define IRQ_STATUS                      0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define IRQ_RAW_STATUS                  0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IRQ_ENABLE                      0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IRQ_ENABLE_SET                  0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define IRQ_ENABLE_CLEAR                0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define INT_SOFT_SET                    0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define INT_SOFT_CLEAR                  0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define FIQ_STATUS                      0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define FIQ_RAW_STATUS                  0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define FIQ_ENABLE                      0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define FIQ_ENABLE_SET                  0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define FIQ_ENABLE_CLEAR                0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)  * LED's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define GREEN_LED                       0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define YELLOW_LED                      0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define RED_LED                         0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define GREEN_LED_2                     0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define ALL_LEDS                        0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define LED_BANK                        INTEGRATOR_DBG_LEDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)  *  Timer definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)  *  Only use timer 1 & 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)  *  (both run at 24MHz and will need the clock divider set to 16).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)  *  Timer 0 runs at bus frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define INTEGRATOR_TIMER0_BASE          INTEGRATOR_CT_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define INTEGRATOR_TIMER1_BASE          (INTEGRATOR_CT_BASE + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define INTEGRATOR_TIMER2_BASE          (INTEGRATOR_CT_BASE + 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define INTEGRATOR_CSR_BASE             0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define INTEGRATOR_CSR_SIZE             0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #endif /* INTEGRATOR_HARDWARE_H */