Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * access the core module control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) u32 cm_get(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) void cm_control(u32, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) struct device_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) void cm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) void cm_clear_irqs(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CM_CTRL_LED			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CM_CTRL_nMBDET			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CM_CTRL_REMAP			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * Integrator/AP,PP2 specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CM_CTRL_HIGHVECTORS		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CM_CTRL_BIGENDIAN		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CM_CTRL_FASTBUS			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CM_CTRL_SYNC			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * ARM926/946/966 Integrator/CP specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CM_CTRL_LCDBIASEN		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CM_CTRL_LCDBIASUP		(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CM_CTRL_LCDBIASDN		(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CM_CTRL_LCDMUXSEL_MASK		(7 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CM_CTRL_LCDMUXSEL_GENLCD	(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CM_CTRL_LCDMUXSEL_VGA565_TFT555	(2 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CM_CTRL_LCDMUXSEL_SHARPLCD	(3 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CM_CTRL_LCDMUXSEL_VGA555_TFT555	(4 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CM_CTRL_LCDEN0			(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CM_CTRL_LCDEN1			(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CM_CTRL_STATIC1			(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CM_CTRL_STATIC2			(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CM_CTRL_STATIC			(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CM_CTRL_n24BITEN		(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CM_CTRL_EBIWP			(1 << 20)