^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "irq-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *****************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * TZIC Registers *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *****************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TZIC_INTCNTL 0x0000 /* Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TZIC_INTTYPE 0x0004 /* Controller Type register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TZIC_PND0 0x0D00 /* Pending Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TZIC_HIPND(i) (0x0D80+ ((i) << 2)) /* High Priority Pending Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static void __iomem *tzic_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TZIC_NUM_IRQS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #ifdef CONFIG_FIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int tzic_set_irq_fiq(unsigned int hwirq, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int index, mask, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) index = hwirq >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (unlikely(index >= 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mask = 1U << (hwirq & 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) value &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) imx_writel(value, tzic_base + TZIC_INTSEC0(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define tzic_set_irq_fiq NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void tzic_irq_suspend(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int idx = d->hwirq >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void tzic_irq_resume(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int idx = d->hwirq >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) tzic_base + TZIC_WAKEUP0(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define tzic_irq_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define tzic_irq_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static struct mxc_extra_irq tzic_extra_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #ifdef CONFIG_FIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .set_irq_fiq = tzic_set_irq_fiq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static __init void tzic_init_gc(int idx, unsigned int irq_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) gc->private = &tzic_extra_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) gc->wake_enabled = IRQ_MSK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ct->chip.irq_mask = irq_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ct->chip.irq_set_wake = irq_gc_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ct->chip.irq_suspend = tzic_irq_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ct->chip.irq_resume = tzic_irq_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ct->regs.disable = TZIC_ENCLEAR0(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ct->regs.enable = TZIC_ENSET0(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int i, irqofs, handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) stat = imx_readl(tzic_base + TZIC_HIPND(i)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) imx_readl(tzic_base + TZIC_INTSEC0(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) while (stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) irqofs = fls(stat) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) handle_domain_irq(domain, irqofs + i * 32, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) stat &= ~(1 << irqofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) } while (handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * This function initializes the TZIC hardware and disables all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * interrupts. It registers the interrupt enable and disable functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * to the kernel for each interrupt source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int __init tzic_init_dt(struct device_node *np, struct device_node *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tzic_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) WARN_ON(!tzic_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* put the TZIC into the reset value with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * all interrupts disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) i = imx_readl(tzic_base + TZIC_INTCNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) imx_writel(0x80010001, tzic_base + TZIC_INTCNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) imx_writel(0x1f, tzic_base + TZIC_PRIOMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) imx_writel(0x02, tzic_base + TZIC_SYNCCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) imx_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) imx_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* all IRQ no FIQ Warning :: No selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) WARN_ON(irq_base < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) &irq_domain_simple_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) WARN_ON(!domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) for (i = 0; i < 4; i++, irq_base += 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) tzic_init_gc(i, irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) set_handle_irq(tzic_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #ifdef CONFIG_FIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Initialize FIQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) init_FIQ(FIQ_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) IRQCHIP_DECLARE(tzic, "fsl,tzic", tzic_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * tzic_enable_wake() - enable wakeup interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @return 0 if successful; non-zero otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * This function provides an interrupt synchronization point that is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * by tzic enabled platforms before entering imx specific low power modes (ie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int tzic_enable_wake(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) imx_writel(1, tzic_base + TZIC_DSMINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tzic_base + TZIC_WAKEUP0(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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