^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1999 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2000 Deep Blue Solutions Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/system_misc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/proc-fns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static void __iomem *wdog_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct clk *wdog_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int wcr_enable = (1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Reset the system. It is called by machine_restart().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void mxc_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (!wdog_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) goto reset_fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (!IS_ERR(wdog_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) clk_enable(wdog_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Assert SRS signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) imx_writew(wcr_enable, wdog_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * written twice), we add another two writes to ensure there must be at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * least two writes happen in the same one 32kHz clock period. We save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * the target check here, since the writes shouldn't be a huge burden
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * for other platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) imx_writew(wcr_enable, wdog_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) imx_writew(wcr_enable, wdog_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* wait for reset to assert... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mdelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* delay to allow the serial port to show the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mdelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) reset_fallback:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* we'll take a jump through zero as a poor second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) soft_restart(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __init mxc_arch_reset_init(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) wdog_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (IS_ERR(wdog_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pr_warn("%s: failed to get wdog clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) clk_prepare(wdog_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #ifdef CONFIG_SOC_IMX1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void __init imx1_reset_init(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) wcr_enable = (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mxc_arch_reset_init(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void __init imx_init_l2cache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void __iomem *l2x0_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) l2x0_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (!l2x0_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) goto put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Configure the L2 PREFETCH and POWER registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) val |= L310_PREFETCH_CTRL_DBL_LINEFILL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) L310_PREFETCH_CTRL_INSTR_PREFETCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) L310_PREFETCH_CTRL_DATA_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Set perfetch offset to improve performance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) val &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) val |= 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) iounmap(l2x0_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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