^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2014 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * ==================== low level suspend ====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Better to follow below rules to use ARM registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * r0: pm_info structure address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * r1 ~ r4: for saving pm_info members;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * r5 ~ r10: free registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * r11: io base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * suspend ocram space layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * ======================== high address ======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * imx6_suspend code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * PM_INFO structure(imx6_cpu_pm_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * ======================== low address =======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Below offsets are based on struct imx6_cpu_pm_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * which defined in arch/arm/mach-imx/pm-imx6q.c, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * structure contains necessary pm info for low level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * suspend related code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PM_INFO_PBASE_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PM_INFO_RESUME_ADDR_OFFSET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PM_INFO_DDR_TYPE_OFFSET 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PM_INFO_PM_INFO_SIZE_OFFSET 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PM_INFO_MX6Q_SRC_P_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PM_INFO_MX6Q_SRC_V_OFFSET 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PM_INFO_MX6Q_CCM_P_OFFSET 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PM_INFO_MX6Q_CCM_V_OFFSET 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PM_INFO_MX6Q_GPC_P_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PM_INFO_MX6Q_GPC_V_OFFSET 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PM_INFO_MX6Q_L2_P_OFFSET 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PM_INFO_MX6Q_L2_V_OFFSET 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PM_INFO_MMDC_IO_NUM_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PM_INFO_MMDC_IO_VAL_OFFSET 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MX6Q_SRC_GPR1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MX6Q_SRC_GPR2 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MX6Q_MMDC_MAPSR 0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MX6Q_MMDC_MPDGCTRL0 0x83c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MX6Q_GPC_IMR1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MX6Q_GPC_IMR2 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MX6Q_GPC_IMR3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MX6Q_GPC_IMR4 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MX6Q_CCM_CCR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .align 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .arm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .macro sync_l2_cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* sync L2 cache to drain L2's buffers to DRAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) teq r11, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) beq 6f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mov r6, #0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) str r6, [r11, #L2X0_CACHE_SYNC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ldr r6, [r11, #L2X0_CACHE_SYNC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ands r6, r6, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bne 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .macro resume_mmdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* restore MMDC IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) cmp r5, #0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) add r7, r7, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ldr r8, [r7], #0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ldr r9, [r7], #0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) str r9, [r11, r8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) subs r6, r6, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) bne 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) cmp r5, #0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) cmp r3, #IMX_DDR_TYPE_LPDDR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) bne 4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* reset read FIFO, RST_RD_FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ldr r7, =MX6Q_MMDC_MPDGCTRL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ldr r6, [r11, r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) orr r6, r6, #(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) str r6, [r11, r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ldr r6, [r11, r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ands r6, r6, #(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bne 2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* reset FIFO a second time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ldr r6, [r11, r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) orr r6, r6, #(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) str r6, [r11, r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ldr r6, [r11, r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ands r6, r6, #(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bne 3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* let DDR out of self-refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ldr r7, [r11, #MX6Q_MMDC_MAPSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bic r7, r7, #(1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) str r7, [r11, #MX6Q_MMDC_MAPSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ldr r7, [r11, #MX6Q_MMDC_MAPSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ands r7, r7, #(1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) bne 5b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* enable DDR auto power saving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ldr r7, [r11, #MX6Q_MMDC_MAPSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) bic r7, r7, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) str r7, [r11, #MX6Q_MMDC_MAPSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ENTRY(imx6_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * counting the resume address in iram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * to set it in SRC register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ldr r6, =imx6_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ldr r7, =resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) sub r7, r7, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) add r8, r1, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) add r9, r8, r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * make sure TLB contain the addr we want,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * as we will access them after MMDC IO floated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ldr r6, [r11, #0x0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ldr r6, [r11, #0x0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ldr r6, [r11, #0x0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* use r11 to store the IO address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* store physical resume addr and pm_info address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) str r9, [r11, #MX6Q_SRC_GPR1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) str r1, [r11, #MX6Q_SRC_GPR2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* need to sync L2 cache before DSM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) sync_l2_cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * put DDR explicitly into self-refresh and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * disable automatic power savings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ldr r7, [r11, #MX6Q_MMDC_MAPSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) orr r7, r7, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) str r7, [r11, #MX6Q_MMDC_MAPSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* make the DDR explicitly enter self-refresh. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ldr r7, [r11, #MX6Q_MMDC_MAPSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) orr r7, r7, #(1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) str r7, [r11, #MX6Q_MMDC_MAPSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) poll_dvfs_set:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ldr r7, [r11, #MX6Q_MMDC_MAPSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ands r7, r7, #(1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) beq poll_dvfs_set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ldr r6, =0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) add r8, r8, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* LPDDR2's last 3 IOs need special setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) cmp r3, #IMX_DDR_TYPE_LPDDR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) subeq r7, r7, #0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) set_mmdc_io_lpm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ldr r9, [r8], #0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) str r6, [r11, r9]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) subs r7, r7, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) bne set_mmdc_io_lpm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) cmp r3, #IMX_DDR_TYPE_LPDDR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) bne set_mmdc_io_lpm_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ldr r6, =0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ldr r9, [r8], #0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) str r6, [r11, r9]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ldr r9, [r8], #0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) str r6, [r11, r9]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ldr r6, =0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ldr r9, [r8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) str r6, [r11, r9]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) set_mmdc_io_lpm_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * mask all GPC interrupts before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * enabling the RBC counters to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * avoid the counter starting too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * early if an interupt is already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ldr r6, [r11, #MX6Q_GPC_IMR1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ldr r7, [r11, #MX6Q_GPC_IMR2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ldr r8, [r11, #MX6Q_GPC_IMR3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ldr r9, [r11, #MX6Q_GPC_IMR4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ldr r10, =0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) str r10, [r11, #MX6Q_GPC_IMR1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) str r10, [r11, #MX6Q_GPC_IMR2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) str r10, [r11, #MX6Q_GPC_IMR3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) str r10, [r11, #MX6Q_GPC_IMR4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * enable the RBC bypass counter here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * to hold off the interrupts. RBC counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * = 32 (1ms), Minimum RBC delay should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * 400us for the analog LDOs to power down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ldr r10, [r11, #MX6Q_CCM_CCR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) bic r10, r10, #(0x3f << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) orr r10, r10, #(0x20 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) str r10, [r11, #MX6Q_CCM_CCR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* enable the counter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ldr r10, [r11, #MX6Q_CCM_CCR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) orr r10, r10, #(0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) str r10, [r11, #MX6Q_CCM_CCR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* unmask all the GPC interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) str r6, [r11, #MX6Q_GPC_IMR1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) str r7, [r11, #MX6Q_GPC_IMR2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) str r8, [r11, #MX6Q_GPC_IMR3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) str r9, [r11, #MX6Q_GPC_IMR4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * now delay for a short while (3usec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * ARM is at 1GHz at this point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * so a short loop should be enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * this delay is required to ensure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * the RBC counter can start counting in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * case an interrupt is already pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * or in case an interrupt arrives just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * as ARM is about to assert DSM_request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ldr r6, =2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) rbc_loop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) subs r6, r6, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) bne rbc_loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Zzz, enter stop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * run to here means there is pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * wakeup source, system should auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * resume, we need to restore MMDC IO first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mov r5, #0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) resume_mmdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* return to suspend finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) resume:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* invalidate L1 I-cache first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mov r6, #0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mcr p15, 0, r6, c7, c5, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mcr p15, 0, r6, c7, c5, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* enable the Icache and branch prediction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mov r6, #0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mcr p15, 0, r6, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* get physical resume address from pm_info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* clear core0's entry and parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mov r7, #0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) str r7, [r11, #MX6Q_SRC_GPR1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) str r7, [r11, #MX6Q_SRC_GPR2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mov r5, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) resume_mmdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ENDPROC(imx6_suspend)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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