^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2011-2014 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2011 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/genalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqchip/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/fncpy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/proc-fns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/tlb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CCR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BM_CCR_WB_COUNT (0x7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BM_CCR_RBC_EN (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLPCR 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BP_CLPCR_LPM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BM_CLPCR_LPM (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BM_CLPCR_SBYOS (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BM_CLPCR_VSTBY (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BP_CLPCR_STBY_COUNT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BM_CLPCR_STBY_COUNT (0x3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CGPR 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MX6Q_SUSPEND_OCRAM_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MX6_MAX_MMDC_IO_NUM 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void __iomem *ccm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void __iomem *suspend_ocram_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * suspend ocram space layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * ======================== high address ======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * imx6_suspend code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * PM_INFO structure(imx6_cpu_pm_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * ======================== low address =======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct imx6_pm_base {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) phys_addr_t pbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void __iomem *vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct imx6_pm_socdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 ddr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const char *mmdc_compat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const char *src_compat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const char *iomuxc_compat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const char *gpc_compat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const char *pl310_compat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const u32 mmdc_io_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const u32 *mmdc_io_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const u32 imx6q_mmdc_io_offset[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0x74c, /* GPR_ADDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const u32 imx6dl_mmdc_io_offset[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 0x74c, /* GPR_ADDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const u32 imx6sl_mmdc_io_offset[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const u32 imx6sll_mmdc_io_offset[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const u32 imx6sx_mmdc_io_offset[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const u32 imx6ul_mmdc_io_offset[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 0x494, 0x4b0, /* MODE_CTL, MODE, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .mmdc_compat = "fsl,imx6q-mmdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .src_compat = "fsl,imx6q-src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .iomuxc_compat = "fsl,imx6q-iomuxc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .gpc_compat = "fsl,imx6q-gpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .pl310_compat = "arm,pl310-cache",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .mmdc_io_offset = imx6q_mmdc_io_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .mmdc_compat = "fsl,imx6q-mmdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .src_compat = "fsl,imx6q-src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .iomuxc_compat = "fsl,imx6dl-iomuxc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .gpc_compat = "fsl,imx6q-gpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .pl310_compat = "arm,pl310-cache",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .mmdc_io_offset = imx6dl_mmdc_io_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .mmdc_compat = "fsl,imx6sl-mmdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .src_compat = "fsl,imx6sl-src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .iomuxc_compat = "fsl,imx6sl-iomuxc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .gpc_compat = "fsl,imx6sl-gpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .pl310_compat = "arm,pl310-cache",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .mmdc_io_offset = imx6sl_mmdc_io_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct imx6_pm_socdata imx6sll_pm_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .mmdc_compat = "fsl,imx6sll-mmdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .src_compat = "fsl,imx6sll-src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .iomuxc_compat = "fsl,imx6sll-iomuxc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .gpc_compat = "fsl,imx6sll-gpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .pl310_compat = "arm,pl310-cache",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .mmdc_io_offset = imx6sll_mmdc_io_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .mmdc_compat = "fsl,imx6sx-mmdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .src_compat = "fsl,imx6sx-src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .iomuxc_compat = "fsl,imx6sx-iomuxc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .gpc_compat = "fsl,imx6sx-gpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .pl310_compat = "arm,pl310-cache",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .mmdc_io_offset = imx6sx_mmdc_io_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const struct imx6_pm_socdata imx6ul_pm_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .mmdc_compat = "fsl,imx6ul-mmdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .src_compat = "fsl,imx6ul-src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .iomuxc_compat = "fsl,imx6ul-iomuxc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .gpc_compat = "fsl,imx6ul-gpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .pl310_compat = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .mmdc_io_offset = imx6ul_mmdc_io_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * This structure is for passing necessary data for low level ocram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * definition is changed, the offset definition in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * otherwise, the suspend to ocram function will be broken!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct imx6_cpu_pm_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) phys_addr_t pbase; /* The physical address of pm_info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) phys_addr_t resume_addr; /* The physical resume address for asm code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 ddr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 pm_info_size; /* Size of pm_info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct imx6_pm_base mmdc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct imx6_pm_base src_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct imx6_pm_base iomuxc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct imx6_pm_base ccm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct imx6_pm_base gpc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct imx6_pm_base l2_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void imx6_set_int_mem_clk_lpm(bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 val = readl_relaxed(ccm_base + CGPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val &= ~BM_CGPR_INT_MEM_CLK_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val |= BM_CGPR_INT_MEM_CLK_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) writel_relaxed(val, ccm_base + CGPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void imx6_enable_rbc(bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * need to mask all interrupts in GPC before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * operating RBC configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) imx_gpc_mask_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* configure RBC enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) val = readl_relaxed(ccm_base + CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) val &= ~BM_CCR_RBC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) val |= enable ? BM_CCR_RBC_EN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) writel_relaxed(val, ccm_base + CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* configure RBC count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val = readl_relaxed(ccm_base + CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) val &= ~BM_CCR_RBC_BYPASS_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) writel(val, ccm_base + CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * need to delay at least 2 cycles of CKIL(32K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * due to hardware design requirement, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * ~61us, here we use 65us for safe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) udelay(65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* restore GPC interrupt mask settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) imx_gpc_restore_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void imx6q_enable_wb(bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* configure well bias enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) val = readl_relaxed(ccm_base + CLPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) val &= ~BM_CLPCR_WB_PER_AT_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) writel_relaxed(val, ccm_base + CLPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* configure well bias count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) val = readl_relaxed(ccm_base + CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) val &= ~BM_CCR_WB_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) val |= enable ? BM_CCR_WB_COUNT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) writel_relaxed(val, ccm_base + CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 val = readl_relaxed(ccm_base + CLPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) val &= ~BM_CLPCR_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case WAIT_CLOCKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case WAIT_UNCLOCKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) val |= 0x1 << BP_CLPCR_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case STOP_POWER_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) val |= 0x2 << BP_CLPCR_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) val &= ~BM_CLPCR_VSTBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) val &= ~BM_CLPCR_SBYOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (cpu_is_imx6sl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) val |= BM_CLPCR_BYPASS_PMIC_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case WAIT_UNCLOCKED_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) val |= 0x1 << BP_CLPCR_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) val &= ~BM_CLPCR_VSTBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) val &= ~BM_CLPCR_SBYOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case STOP_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) val |= 0x2 << BP_CLPCR_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) val |= 0x3 << BP_CLPCR_STBY_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) val |= BM_CLPCR_VSTBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) val |= BM_CLPCR_SBYOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (cpu_is_imx6sl() || cpu_is_imx6sx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) val |= BM_CLPCR_BYPASS_PMIC_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * ERR007265: CCM: When improper low-power sequence is used,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * the SoC enters low power mode before the ARM core executes WFI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Software workaround:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * by setting IOMUX_GPR1_GINT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * 2) Software should then unmask IRQ #32 in GPC before setting CCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * Low-Power mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * 3) Software should mask IRQ #32 right after CCM Low-Power mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * is set (set bits 0-1 of CCM_CLPCR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Note that IRQ #32 is GIC SPI #0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (mode != WAIT_CLOCKED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) imx_gpc_hwirq_unmask(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) writel_relaxed(val, ccm_base + CLPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (mode != WAIT_CLOCKED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) imx_gpc_hwirq_mask(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int imx6q_suspend_finish(unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!imx6_suspend_in_ocram_fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * call low level suspend function in ocram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * as we need to float DDR IO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) local_flush_tlb_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* check if need to flush internal L2 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!((struct imx6_cpu_pm_info *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) suspend_ocram_base)->l2_base.vbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) imx6_suspend_in_ocram_fn(suspend_ocram_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int imx6q_pm_enter(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case PM_SUSPEND_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) imx6_set_lpm(STOP_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) imx6_set_int_mem_clk_lpm(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) imx_gpc_pre_suspend(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (cpu_is_imx6sl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) imx6sl_set_wait_clk(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Zzz ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (cpu_is_imx6sl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) imx6sl_set_wait_clk(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) imx_gpc_post_resume();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) imx6_set_lpm(WAIT_CLOCKED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case PM_SUSPEND_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) imx6_set_lpm(STOP_POWER_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) imx6_set_int_mem_clk_lpm(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) imx6q_enable_wb(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * For suspend into ocram, asm code already take care of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * RBC setting, so we do NOT need to do that here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (!imx6_suspend_in_ocram_fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) imx6_enable_rbc(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) imx_gpc_pre_suspend(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) imx_anatop_pre_suspend();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Zzz ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) cpu_suspend(0, imx6q_suspend_finish);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (cpu_is_imx6q() || cpu_is_imx6dl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) imx_smp_prepare();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) imx_anatop_post_resume();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) imx_gpc_post_resume();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) imx6_enable_rbc(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) imx6q_enable_wb(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) imx6_set_int_mem_clk_lpm(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) imx6_set_lpm(WAIT_CLOCKED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int imx6q_pm_valid(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const struct platform_suspend_ops imx6q_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .enter = imx6q_pm_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .valid = imx6q_pm_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int __init imx6_pm_get_base(struct imx6_pm_base *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) const char *compat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) node = of_find_compatible_node(NULL, NULL, compat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = of_address_to_resource(node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) goto put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) base->pbase = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) base->vbase = ioremap(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (!base->vbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) phys_addr_t ocram_pbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct imx6_cpu_pm_info *pm_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct gen_pool *ocram_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned long ocram_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) const u32 *mmdc_offset_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) suspend_set_ops(&imx6q_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!socdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) pr_warn("%s: invalid argument!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) node = of_find_compatible_node(NULL, NULL, "mmio-sram");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pr_warn("%s: failed to find ocram node!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pdev = of_find_device_by_node(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) pr_warn("%s: failed to find ocram device!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) goto put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ocram_pool = gen_pool_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!ocram_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pr_warn("%s: ocram pool unavailable!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) goto put_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!ocram_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pr_warn("%s: unable to alloc ocram!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) goto put_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MX6Q_SUSPEND_OCRAM_SIZE, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) memset(suspend_ocram_base, 0, sizeof(*pm_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pm_info = suspend_ocram_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pm_info->pbase = ocram_pbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pm_info->resume_addr = __pa_symbol(v7_cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pm_info->pm_info_size = sizeof(*pm_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * ccm physical address is not used by asm code currently,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * so get ccm virtual address directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) pm_info->ccm_base.vbase = ccm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) goto put_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pr_warn("%s: failed to get src base %d!\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) goto src_map_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) goto iomuxc_map_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) goto gpc_map_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (socdata->pl310_compat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pr_warn("%s: failed to get pl310-cache base %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) goto pl310_cache_map_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pm_info->ddr_type = imx_mmdc_get_ddr_type();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pm_info->mmdc_io_num = socdata->mmdc_io_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mmdc_offset_array = socdata->mmdc_io_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) for (i = 0; i < pm_info->mmdc_io_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pm_info->mmdc_io_val[i][0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mmdc_offset_array[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pm_info->mmdc_io_val[i][1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) readl_relaxed(pm_info->iomuxc_base.vbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mmdc_offset_array[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) imx6_suspend_in_ocram_fn = fncpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) suspend_ocram_base + sizeof(*pm_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) &imx6_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) goto put_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pl310_cache_map_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) iounmap(pm_info->gpc_base.vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) gpc_map_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) iounmap(pm_info->iomuxc_base.vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) iomuxc_map_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) iounmap(pm_info->src_base.vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) src_map_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) iounmap(pm_info->mmdc_base.vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) put_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) put_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static void __init imx6_pm_common_init(const struct imx6_pm_socdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) *socdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct regmap *gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) WARN_ON(!ccm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (IS_ENABLED(CONFIG_SUSPEND)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = imx6q_suspend_init(socdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pr_warn("%s: No DDR LPM support with suspend %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * This is for SW workaround step #1 of ERR007265, see comments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * in imx6_set_lpm for details of this errata.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * Force IOMUXC irq pending, so that the interrupt to GPC can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * used to deassert dsm_request signal when the signal gets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * asserted unexpectedly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (!IS_ERR(gpr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) IMX6Q_GPR1_GINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static void imx6_pm_stby_poweroff(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) gic_cpu_if_down(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) imx6_set_lpm(STOP_POWER_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) imx6q_suspend_finish(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) mdelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pr_emerg("Unable to poweroff system\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static int imx6_pm_stby_poweroff_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (pm_power_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pr_warn("%s: pm_power_off already claimed %p %ps!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) __func__, pm_power_off, pm_power_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) pm_power_off = imx6_pm_stby_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) void __init imx6_pm_ccm_init(const char *ccm_compat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) np = of_find_compatible_node(NULL, NULL, ccm_compat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ccm_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) BUG_ON(!ccm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * Initialize CCM_CLPCR_LPM into RUN mode to avoid ARM core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * clock being shut down unexpectedly by WAIT mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) val = readl_relaxed(ccm_base + CLPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) val &= ~BM_CLPCR_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) writel_relaxed(val, ccm_base + CLPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (of_property_read_bool(np, "fsl,pmic-stby-poweroff"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) imx6_pm_stby_poweroff_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) void __init imx6q_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) imx6_pm_common_init(&imx6q_pm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) void __init imx6dl_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) imx6_pm_common_init(&imx6dl_pm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) void __init imx6sl_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct regmap *gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (cpu_is_imx6sl()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) imx6_pm_common_init(&imx6sl_pm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) imx6_pm_common_init(&imx6sll_pm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (!IS_ERR(gpr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) regmap_update_bits(gpr, IOMUXC_GPR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) void __init imx6sx_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) imx6_pm_common_init(&imx6sx_pm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) void __init imx6ul_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) imx6_pm_common_init(&imx6ul_pm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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