^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2011 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2011 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/smp_scu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 g_diag_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static void __iomem *scu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static struct map_desc scu_io_desc __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* .virtual and .pfn are run-time assigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .length = SZ_4K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void __init imx_scu_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Get SCU base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) scu_io_desc.virtual = IMX_IO_P2V(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) scu_io_desc.pfn = __phys_to_pfn(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) iotable_init(&scu_io_desc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) scu_base = IMX_IO_ADDRESS(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) imx_set_cpu_jump(cpu, v7_secondary_startup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) imx_enable_cpu(cpu, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Initialise the CPU possible map early - this describes the CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * which may be present or become present in the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void __init imx_smp_init_cpus(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int i, ncores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ncores = scu_get_core_count(scu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) for (i = ncores; i < NR_CPUS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) set_cpu_possible(i, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void imx_smp_prepare(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) scu_enable(scu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) imx_smp_prepare();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * The diagnostic register holds the errata bits. Mostly bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * does not bring up secondary cores, so that when errata bits are set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * in bootloader, they are set only for boot cpu. But on a SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * configuration, it should be equally done on every single core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Read the register from boot cpu here, and will replicate it into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * secondary cores when booting them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) sync_cache_w(&g_diag_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) const struct smp_operations imx_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .smp_init_cpus = imx_smp_init_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .smp_prepare_cpus = imx_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .smp_boot_secondary = imx_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .cpu_die = imx_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .cpu_kill = imx_cpu_kill,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DCFG_CCSR_SCRATCHRW1 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) arch_send_wakeup_ipi_mask(cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void __iomem *dcfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned long paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dcfg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) BUG_ON(!dcfg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) paddr = __pa_symbol(secondary_startup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) iounmap(dcfg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct smp_operations ls1021a_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .smp_prepare_cpus = ls1021a_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .smp_boot_secondary = ls1021a_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags