Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef __MACH_MX3x_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define __MACH_MX3x_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * MX31 memory map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Virt		Phys		Size	What
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * FC000000	43F00000	1M	AIPS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * FC100000	50000000	1M	SPBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * FC200000	53F00000	1M	AIPS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * FC500000	60000000	128M	ROMPATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * FC400000	68000000	128M	AVIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *         	70000000	256M	IPU (MAX M2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *         	80000000	256M	CSD0 SDRAM/DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *         	90000000	256M	CSD1 SDRAM/DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *         	A0000000	128M	CS0 Flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *         	A8000000	128M	CS1 Flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *         	B0000000	32M	CS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *         	B2000000	32M	CS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * F4000000	B4000000	32M	CS4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *         	B6000000	32M	CS5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * FC320000	B8000000	64K	NAND, SDRAM, WEIM, M3IF, EMI controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *         	C0000000	64M	PCMCIA/CF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * L2CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MX3x_L2CC_BASE_ADDR		0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MX3x_L2CC_SIZE			SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * AIPS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MX3x_AIPS1_BASE_ADDR		0x43f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MX3x_AIPS1_SIZE			SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MX3x_MAX_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x04000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MX3x_EVTMON_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x08000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MX3x_CLKCTL_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x0c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MX3x_ETB_SLOT4_BASE_ADDR		(MX3x_AIPS1_BASE_ADDR + 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MX3x_ETB_SLOT5_BASE_ADDR		(MX3x_AIPS1_BASE_ADDR + 0x14000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MX3x_ECT_CTIO_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x18000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MX3x_I2C_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x80000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MX3x_I2C3_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x84000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MX3x_UART1_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x90000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MX3x_UART2_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x94000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MX3x_I2C2_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x98000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MX3x_OWIRE_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x9c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MX3x_SSI1_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0xa0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MX3x_CSPI1_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0xa4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MX3x_KPP_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0xa8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MX3x_IOMUXC_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0xac000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MX3x_ECT_IP1_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0xb8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MX3x_ECT_IP2_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0xbc000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * SPBA global module enabled #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MX3x_SPBA0_BASE_ADDR		0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MX3x_SPBA0_SIZE			SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MX3x_UART3_BASE_ADDR			(MX3x_SPBA0_BASE_ADDR + 0x0c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MX3x_CSPI2_BASE_ADDR			(MX3x_SPBA0_BASE_ADDR + 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MX3x_SSI2_BASE_ADDR			(MX3x_SPBA0_BASE_ADDR + 0x14000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MX3x_ATA_DMA_BASE_ADDR			(MX3x_SPBA0_BASE_ADDR + 0x20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MX3x_MSHC1_BASE_ADDR			(MX3x_SPBA0_BASE_ADDR + 0x24000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MX3x_SPBA_CTRL_BASE_ADDR		(MX3x_SPBA0_BASE_ADDR + 0x3c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * AIPS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MX3x_AIPS2_BASE_ADDR		0x53f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MX3x_AIPS2_SIZE			SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MX3x_CCM_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0x80000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MX3x_GPT1_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0x90000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MX3x_EPIT1_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0x94000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define MX3x_EPIT2_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0x98000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define MX3x_GPIO3_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xa4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define MX3x_SCC_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xac000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define MX3x_RNGA_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xb0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MX3x_IPU_CTRL_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xc0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MX3x_AUDMUX_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xc4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define MX3x_GPIO1_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xcc000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MX3x_GPIO2_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xd0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define MX3x_SDMA_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xd4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define MX3x_RTC_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xd8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define MX3x_WDOG_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xdc000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define MX3x_PWM_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xe0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define MX3x_RTIC_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xec000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * ROMP and AVIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MX3x_ROMP_BASE_ADDR		0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MX3x_ROMP_SIZE			SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MX3x_AVIC_BASE_ADDR		0x68000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MX3x_AVIC_SIZE			SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  * Memory regions and CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MX3x_IPU_MEM_BASE_ADDR		0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MX3x_CSD0_BASE_ADDR		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MX3x_CSD1_BASE_ADDR		0x90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MX3x_CS0_BASE_ADDR		0xa0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MX3x_CS1_BASE_ADDR		0xa8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MX3x_CS2_BASE_ADDR		0xb0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MX3x_CS3_BASE_ADDR		0xb2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MX3x_CS4_BASE_ADDR		0xb4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MX3x_CS4_BASE_ADDR_VIRT		0xf6000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MX3x_CS4_SIZE			SZ_32M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MX3x_CS5_BASE_ADDR		0xb6000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MX3x_CS5_BASE_ADDR_VIRT		0xf8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MX3x_CS5_SIZE			SZ_32M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * NAND, SDRAM, WEIM, M3IF, EMI controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MX3x_X_MEMC_BASE_ADDR		0xb8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MX3x_X_MEMC_SIZE		SZ_64K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MX3x_ESDCTL_BASE_ADDR			(MX3x_X_MEMC_BASE_ADDR + 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MX3x_WEIM_BASE_ADDR			(MX3x_X_MEMC_BASE_ADDR + 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MX3x_M3IF_BASE_ADDR			(MX3x_X_MEMC_BASE_ADDR + 0x3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MX3x_EMI_CTL_BASE_ADDR			(MX3x_X_MEMC_BASE_ADDR + 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MX3x_PCMCIA_CTL_BASE_ADDR		MX3x_EMI_CTL_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MX3x_PCMCIA_MEM_BASE_ADDR	0xbc000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * Interrupt numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MX3x_INT_I2C3		(NR_IRQS_LEGACY + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MX3x_INT_I2C2		(NR_IRQS_LEGACY + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MX3x_INT_RTIC		(NR_IRQS_LEGACY + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MX3x_INT_I2C		(NR_IRQS_LEGACY + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MX3x_INT_CSPI2		(NR_IRQS_LEGACY + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MX3x_INT_CSPI1		(NR_IRQS_LEGACY + 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MX3x_INT_ATA		(NR_IRQS_LEGACY + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MX3x_INT_UART3		(NR_IRQS_LEGACY + 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MX3x_INT_IIM		(NR_IRQS_LEGACY + 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MX3x_INT_RNGA		(NR_IRQS_LEGACY + 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MX3x_INT_EVTMON		(NR_IRQS_LEGACY + 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MX3x_INT_KPP		(NR_IRQS_LEGACY + 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MX3x_INT_RTC		(NR_IRQS_LEGACY + 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MX3x_INT_PWM		(NR_IRQS_LEGACY + 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MX3x_INT_EPIT2		(NR_IRQS_LEGACY + 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MX3x_INT_EPIT1		(NR_IRQS_LEGACY + 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MX3x_INT_GPT		(NR_IRQS_LEGACY + 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MX3x_INT_POWER_FAIL	(NR_IRQS_LEGACY + 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MX3x_INT_UART2		(NR_IRQS_LEGACY + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MX3x_INT_NANDFC		(NR_IRQS_LEGACY + 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MX3x_INT_SDMA		(NR_IRQS_LEGACY + 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MX3x_INT_MSHC1		(NR_IRQS_LEGACY + 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MX3x_INT_IPU_ERR	(NR_IRQS_LEGACY + 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MX3x_INT_IPU_SYN	(NR_IRQS_LEGACY + 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MX3x_INT_UART1		(NR_IRQS_LEGACY + 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MX3x_INT_ECT		(NR_IRQS_LEGACY + 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MX3x_INT_SCC_SCM	(NR_IRQS_LEGACY + 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MX3x_INT_SCC_SMN	(NR_IRQS_LEGACY + 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MX3x_INT_GPIO2		(NR_IRQS_LEGACY + 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MX3x_INT_GPIO1		(NR_IRQS_LEGACY + 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MX3x_INT_WDOG		(NR_IRQS_LEGACY + 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MX3x_INT_GPIO3		(NR_IRQS_LEGACY + 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MX3x_INT_EXT_POWER	(NR_IRQS_LEGACY + 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MX3x_INT_EXT_TEMPER	(NR_IRQS_LEGACY + 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MX3x_INT_EXT_SENSOR60	(NR_IRQS_LEGACY + 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MX3x_INT_EXT_SENSOR61	(NR_IRQS_LEGACY + 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MX3x_INT_EXT_WDOG	(NR_IRQS_LEGACY + 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MX3x_INT_EXT_TV		(NR_IRQS_LEGACY + 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MX3x_PROD_SIGNATURE		0x1	/* For MX31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif /* ifndef __MACH_MX3x_H__ */