^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __MACH_MX35_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __MACH_MX35_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define MX35_AIPS1_BASE_ADDR 0x43f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define MX35_AIPS1_SIZE SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define MX35_SPBA0_BASE_ADDR 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define MX35_SPBA0_SIZE SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define MX35_AIPS2_BASE_ADDR 0x53f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MX35_AIPS2_SIZE SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MX35_AVIC_BASE_ADDR 0x68000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MX35_AVIC_SIZE SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MX35_X_MEMC_BASE_ADDR 0xb8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MX35_X_MEMC_SIZE SZ_64K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MX35_IO_P2V(x) IMX_IO_P2V(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #endif /* ifndef __MACH_MX35_H__ */