^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This contains hardware definitions that are common between i.MX21 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * i.MX27.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __MACH_MX2x_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __MACH_MX2x_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* The following addresses are common between i.MX21 and i.MX27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MX2x_AIPI_BASE_ADDR 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MX2x_AIPI_SIZE SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MX2x_AVIC_BASE_ADDR 0x10040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MX2x_SAHB1_BASE_ADDR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MX2x_SAHB1_SIZE SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* fixed interrupt numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MX2x_INT_I2C (NR_IRQS_LEGACY + 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MX2x_INT_KPP (NR_IRQS_LEGACY + 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MX2x_INT_RTC (NR_IRQS_LEGACY + 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MX2x_INT_PWM (NR_IRQS_LEGACY + 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MX2x_INT_CSI (NR_IRQS_LEGACY + 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* fixed DMA request numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MX2x_DMA_REQ_CSPI3_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MX2x_DMA_REQ_CSPI3_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MX2x_DMA_REQ_EXT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MX2x_DMA_REQ_SDHC2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MX2x_DMA_REQ_SDHC1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MX2x_DMA_REQ_SSI2_RX0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MX2x_DMA_REQ_SSI2_TX0 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MX2x_DMA_REQ_SSI2_RX1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MX2x_DMA_REQ_SSI2_TX1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MX2x_DMA_REQ_SSI1_RX0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MX2x_DMA_REQ_SSI1_TX0 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MX2x_DMA_REQ_SSI1_RX1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MX2x_DMA_REQ_SSI1_TX1 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MX2x_DMA_REQ_CSPI2_RX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MX2x_DMA_REQ_CSPI2_TX 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MX2x_DMA_REQ_CSPI1_RX 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MX2x_DMA_REQ_CSPI1_TX 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MX2x_DMA_REQ_UART4_RX 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MX2x_DMA_REQ_UART4_TX 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MX2x_DMA_REQ_UART3_RX 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MX2x_DMA_REQ_UART3_TX 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MX2x_DMA_REQ_UART2_RX 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MX2x_DMA_REQ_UART2_TX 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MX2x_DMA_REQ_UART1_RX 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MX2x_DMA_REQ_UART1_TX 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MX2x_DMA_REQ_CSI_STAT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MX2x_DMA_REQ_CSI_RX 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif /* ifndef __MACH_MX2x_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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