^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2017 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2011,2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/hrtimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MMDC_MAPSR 0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BP_MMDC_MAPSR_PSD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BP_MMDC_MAPSR_PSS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MMDC_MDMISC 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BM_MMDC_MDMISC_DDR_TYPE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BP_MMDC_MDMISC_DDR_TYPE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TOTAL_CYCLES 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BUSY_CYCLES 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define READ_ACCESSES 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define WRITE_ACCESSES 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define READ_BYTES 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define WRITE_BYTES 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Enables, resets, freezes, overflow profiling*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DBG_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DBG_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DBG_RST 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PRF_FRZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CYC_OVF 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PROFILE_SEL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MMDC_MADPCR0 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MMDC_MADPCR1 0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MMDC_MADPSR0 0x418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MMDC_MADPSR1 0x41C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MMDC_MADPSR2 0x420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MMDC_MADPSR3 0x424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MMDC_MADPSR4 0x428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MMDC_MADPSR5 0x42C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MMDC_NUM_COUNTERS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MMDC_FLAG_PROFILE_SEL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MMDC_PRF_AXI_ID_CLEAR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int ddr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct fsl_mmdc_devtype_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const struct fsl_mmdc_devtype_data imx6q_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const struct fsl_mmdc_devtype_data imx6qp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .flags = MMDC_FLAG_PROFILE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const struct of_device_id imx_mmdc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #ifdef CONFIG_PERF_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static enum cpuhp_state cpuhp_mmdc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static DEFINE_IDA(mmdc_ida);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PMU_EVENT_ATTR_STRING(write-bytes, mmdc_pmu_write_bytes, "event=0x05")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PMU_EVENT_ATTR_STRING(write-bytes.unit, mmdc_pmu_write_bytes_unit, "MB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PMU_EVENT_ATTR_STRING(write-bytes.scale, mmdc_pmu_write_bytes_scale, "0.000001");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct mmdc_pmu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct pmu pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void __iomem *mmdc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) cpumask_t cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct hrtimer hrtimer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int active_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct perf_event *mmdc_events[MMDC_NUM_COUNTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct hlist_node node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct fsl_mmdc_devtype_data *devtype_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct clk *mmdc_ipg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Polling period is set to one second, overflow of total-cycles (the fastest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * increasing counter) takes ten seconds so one second is safe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static unsigned int mmdc_pmu_poll_period_us = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) module_param_named(pmu_pmu_poll_period_us, mmdc_pmu_poll_period_us, uint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static ktime_t mmdc_pmu_timer_period(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return ns_to_ktime((u64)mmdc_pmu_poll_period_us * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static ssize_t mmdc_pmu_cpumask_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct mmdc_pmu *pmu_mmdc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return cpumap_print_to_pagebuf(true, buf, &pmu_mmdc->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct device_attribute mmdc_pmu_cpumask_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __ATTR(cpumask, S_IRUGO, mmdc_pmu_cpumask_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct attribute *mmdc_pmu_cpumask_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) &mmdc_pmu_cpumask_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct attribute_group mmdc_pmu_cpumask_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .attrs = mmdc_pmu_cpumask_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct attribute *mmdc_pmu_events_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) &mmdc_pmu_total_cycles.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) &mmdc_pmu_busy_cycles.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) &mmdc_pmu_read_accesses.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) &mmdc_pmu_write_accesses.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) &mmdc_pmu_read_bytes.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) &mmdc_pmu_read_bytes_unit.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) &mmdc_pmu_read_bytes_scale.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) &mmdc_pmu_write_bytes.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) &mmdc_pmu_write_bytes_unit.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) &mmdc_pmu_write_bytes_scale.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct attribute_group mmdc_pmu_events_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "events",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .attrs = mmdc_pmu_events_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PMU_FORMAT_ATTR(event, "config:0-63");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PMU_FORMAT_ATTR(axi_id, "config1:0-63");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct attribute *mmdc_pmu_format_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) &format_attr_event.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) &format_attr_axi_id.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct attribute_group mmdc_pmu_format_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .name = "format",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .attrs = mmdc_pmu_format_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct attribute_group *attr_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) &mmdc_pmu_events_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) &mmdc_pmu_format_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) &mmdc_pmu_cpumask_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static u32 mmdc_pmu_read_counter(struct mmdc_pmu *pmu_mmdc, int cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void __iomem *mmdc_base, *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mmdc_base = pmu_mmdc->mmdc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) switch (cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case TOTAL_CYCLES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) reg = mmdc_base + MMDC_MADPSR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case BUSY_CYCLES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) reg = mmdc_base + MMDC_MADPSR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case READ_ACCESSES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) reg = mmdc_base + MMDC_MADPSR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case WRITE_ACCESSES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) reg = mmdc_base + MMDC_MADPSR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case READ_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) reg = mmdc_base + MMDC_MADPSR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case WRITE_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) reg = mmdc_base + MMDC_MADPSR5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return WARN_ONCE(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "invalid configuration %d for mmdc counter", cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int mmdc_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct mmdc_pmu *pmu_mmdc = hlist_entry_safe(node, struct mmdc_pmu, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!cpumask_test_and_clear_cpu(cpu, &pmu_mmdc->cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) target = cpumask_any_but(cpu_online_mask, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (target >= nr_cpu_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) perf_pmu_migrate_context(&pmu_mmdc->pmu, cpu, target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cpumask_set_cpu(target, &pmu_mmdc->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static bool mmdc_pmu_group_event_is_valid(struct perf_event *event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct pmu *pmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long *used_counters)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int cfg = event->attr.config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (is_software_event(event))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (event->pmu != pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return !test_and_set_bit(cfg, used_counters);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Each event has a single fixed-purpose counter, so we can only have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * single active event for each at any point in time. Here we just check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * for duplicates, and rely on mmdc_pmu_event_init to verify that the HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * event numbers are valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static bool mmdc_pmu_group_is_valid(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct pmu *pmu = event->pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct perf_event *leader = event->group_leader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct perf_event *sibling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned long counter_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) set_bit(leader->attr.config, &counter_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (event != leader) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (!mmdc_pmu_group_event_is_valid(event, pmu, &counter_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) for_each_sibling_event(sibling, leader) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int mmdc_pmu_event_init(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int cfg = event->attr.config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (event->attr.type != event->pmu->type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (event->cpu < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_warn(pmu_mmdc->dev, "Can't provide per-task data!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (event->attr.sample_period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (cfg < 0 || cfg >= MMDC_NUM_COUNTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!mmdc_pmu_group_is_valid(event))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) event->cpu = cpumask_first(&pmu_mmdc->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void mmdc_pmu_event_update(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u64 delta, prev_raw_count, new_raw_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) prev_raw_count = local64_read(&hwc->prev_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) new_raw_count = mmdc_pmu_read_counter(pmu_mmdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) event->attr.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) new_raw_count) != prev_raw_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) local64_add(delta, &event->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void mmdc_pmu_event_start(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) void __iomem *mmdc_base, *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mmdc_base = pmu_mmdc->mmdc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) reg = mmdc_base + MMDC_MADPCR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * hrtimer is required because mmdc does not provide an interrupt so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * polling is necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) hrtimer_start(&pmu_mmdc->hrtimer, mmdc_pmu_timer_period(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) HRTIMER_MODE_REL_PINNED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) local64_set(&hwc->prev_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) writel(DBG_RST, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Write the AXI id parameter to MADPCR1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) val = event->attr.config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) reg = mmdc_base + MMDC_MADPCR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) reg = mmdc_base + MMDC_MADPCR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) val = DBG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) val |= PROFILE_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int mmdc_pmu_event_add(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int cfg = event->attr.config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (flags & PERF_EF_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mmdc_pmu_event_start(event, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (pmu_mmdc->mmdc_events[cfg] != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) pmu_mmdc->mmdc_events[cfg] = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pmu_mmdc->active_events++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) local64_set(&hwc->prev_count, mmdc_pmu_read_counter(pmu_mmdc, cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void mmdc_pmu_event_stop(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) void __iomem *mmdc_base, *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) mmdc_base = pmu_mmdc->mmdc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) reg = mmdc_base + MMDC_MADPCR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) writel(PRF_FRZ, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) reg = mmdc_base + MMDC_MADPCR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) writel(MMDC_PRF_AXI_ID_CLEAR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) mmdc_pmu_event_update(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static void mmdc_pmu_event_del(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int cfg = event->attr.config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pmu_mmdc->mmdc_events[cfg] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pmu_mmdc->active_events--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (pmu_mmdc->active_events == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) hrtimer_cancel(&pmu_mmdc->hrtimer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mmdc_pmu_event_stop(event, PERF_EF_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void mmdc_pmu_overflow_handler(struct mmdc_pmu *pmu_mmdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) for (i = 0; i < MMDC_NUM_COUNTERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct perf_event *event = pmu_mmdc->mmdc_events[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) mmdc_pmu_event_update(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct mmdc_pmu *pmu_mmdc = container_of(hrtimer, struct mmdc_pmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) hrtimer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mmdc_pmu_overflow_handler(pmu_mmdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) hrtimer_forward_now(hrtimer, mmdc_pmu_timer_period());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return HRTIMER_RESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) void __iomem *mmdc_base, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int mmdc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) *pmu_mmdc = (struct mmdc_pmu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .pmu = (struct pmu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .task_ctx_nr = perf_invalid_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .attr_groups = attr_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .event_init = mmdc_pmu_event_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .add = mmdc_pmu_event_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .del = mmdc_pmu_event_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .start = mmdc_pmu_event_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .stop = mmdc_pmu_event_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .read = mmdc_pmu_event_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .mmdc_base = mmdc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .dev = dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .active_events = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mmdc_num = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return mmdc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int imx_mmdc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) perf_pmu_unregister(&pmu_mmdc->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) iounmap(pmu_mmdc->mmdc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) clk_disable_unprepare(pmu_mmdc->mmdc_ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) kfree(pmu_mmdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct clk *mmdc_ipg_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct mmdc_pmu *pmu_mmdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int mmdc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) const struct of_device_id *of_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) of_match_device(imx_mmdc_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pmu_mmdc = kzalloc(sizeof(*pmu_mmdc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!pmu_mmdc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) pr_err("failed to allocate PMU device!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* The first instance registers the hotplug state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!cpuhp_mmdc_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) "perf/arm/mmdc:online", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mmdc_pmu_offline_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) pr_err("cpuhp_setup_state_multi failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) goto pmu_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) cpuhp_mmdc_state = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (mmdc_num == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) name = "mmdc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) name = devm_kasprintf(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) GFP_KERNEL, "mmdc%d", mmdc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pmu_mmdc->hrtimer.function = mmdc_pmu_timer_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) cpumask_set_cpu(raw_smp_processor_id(), &pmu_mmdc->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Register the pmu instance for cpu hotplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) cpuhp_state_add_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = perf_pmu_register(&(pmu_mmdc->pmu), name, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) goto pmu_register_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) platform_set_drvdata(pdev, pmu_mmdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) pmu_register_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) hrtimer_cancel(&pmu_mmdc->hrtimer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pmu_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) kfree(pmu_mmdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define imx_mmdc_remove NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define imx_mmdc_perf_init(pdev, mmdc_base, mmdc_ipg_clk) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int imx_mmdc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) void __iomem *mmdc_base, *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct clk *mmdc_ipg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* the ipg clock is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mmdc_ipg_clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (IS_ERR(mmdc_ipg_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mmdc_ipg_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) err = clk_prepare_enable(mmdc_ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_err(&pdev->dev, "Unable to enable mmdc ipg clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mmdc_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) WARN_ON(!mmdc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) reg = mmdc_base + MMDC_MDMISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Get ddr type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) val = readl_relaxed(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ddr_type = (val & BM_MMDC_MDMISC_DDR_TYPE) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) BP_MMDC_MDMISC_DDR_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) reg = mmdc_base + MMDC_MAPSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* Enable automatic power saving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) val = readl_relaxed(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) val &= ~(1 << BP_MMDC_MAPSR_PSD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) writel_relaxed(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) err = imx_mmdc_perf_init(pdev, mmdc_base, mmdc_ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) iounmap(mmdc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) clk_disable_unprepare(mmdc_ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int imx_mmdc_get_ddr_type(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ddr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static struct platform_driver imx_mmdc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .name = "imx-mmdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .of_match_table = imx_mmdc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .probe = imx_mmdc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .remove = imx_mmdc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int __init imx_mmdc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return platform_driver_register(&imx_mmdc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) postcore_initcall(imx_mmdc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags